powerpc/85xx: Handle the lack of L2 cache on P2040/P2040E

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / cpu_init_nand.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 184cca4c543764d4a5bbc8566a00354176c45a9f..796d3984261e889ef456bf1188897fd7668f08bc 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -25,7 +25,7 @@
 
 void cpu_init_f(void)
 {
-       ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+       fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
        /*
         * LCRR - Clock Ratio Register - set up local bus timing
@@ -33,17 +33,15 @@ void cpu_init_f(void)
         */
        out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
 
-#if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
-       out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
-       out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+       set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+       set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
 #else
-#error  CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
+#error  CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
        ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
-       char *l2srbar;
-       int i;
 
        out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
 
@@ -54,10 +52,5 @@ void cpu_init_f(void)
        /* set L2E=1 & L2SRAM=001 */
        out_be32(&l2cache->l2ctl,
                (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
-
-       /* Initialize L2 SRAM to zero */
-       l2srbar = (char *)CONFIG_SYS_INIT_L2_ADDR;
-       for (i = 0; i < CONFIG_SYS_L2_SIZE; i++)
-               l2srbar[i] = 0;
 #endif
 }