Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / ddr-gen2.c

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index 10f36856de729ef162e9dd0f6411c3de8da83b46..542bc84acf941c44cf3ce8b7b7d2e1ee08d41967 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -15,13 +16,14 @@
 #endif
 
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
-                            unsigned int ctrl_num)
+                            unsigned int ctrl_num, int step)
 {
        unsigned int i;
-#ifdef CONFIG_MPC83xx
-       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
-#else
-       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       uint svr;
 #endif
 
        if (ctrl_num) {
@@ -29,6 +31,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                return;
        }
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+       /*
+        * Set the DDR IO receiver to an acceptable bias point.
+        * Fixed in Rev 2.1.
+        */
+       svr = get_svr();
+       if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+               if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+                  SDRAM_CFG_SDRAM_TYPE_DDR2)
+                       out_be32(&gur->ddrioovcr, 0x90000000);
+               else
+                       out_be32(&gur->ddrioovcr, 0xA8000000);
+       }
+#endif
+
        for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
                if (i == 0) {
                        out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);