]> git.karo-electronics.de Git - karo-tx-uboot.git/blobdiff - arch/powerpc/cpu/mpc85xx/release.S
powerpc/fsl-corenet: work around erratum A004510
[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / release.S
index 1860684c11adf56a75c12677fa45912f93378d06..043d0ff773719313cf197252efba9190abc711fd 100644 (file)
@@ -74,6 +74,33 @@ __secondary_start_page:
        mtspr   977,r3
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
+       mfspr   r3,SPRN_SVR
+       rlwinm  r3,r3,0,0xff
+       li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+       cmpw    r3,r4
+       beq     1f
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
+       li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
+       cmpw    r3,r4
+       beq     1f
+#endif
+
+       /* Not a supported revision affected by erratum */
+       b       2f
+
+1:     /* Erratum says set bits 55:60 to 001001 */
+       msync
+       isync
+       mfspr   r3,976
+       li      r4,0x48
+       rlwimi  r3,r4,0,0x1f8
+       mtspr   976,r3
+       isync
+2:
+#endif
+
        /* Enable branch prediction */
        lis     r3,BUCSR_ENABLE@h
        ori     r3,r3,BUCSR_ENABLE@l
@@ -163,6 +190,12 @@ __secondary_start_page:
        cmpw    r3,r5
        bge     2f
 1:
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+       lis     r3,toreset(enable_cpu_a011_workaround)@ha
+       lwz     r3,toreset(enable_cpu_a011_workaround)@l(r3)
+       cmpwi   r3,0
+       beq     2f
+#endif
        mfspr   r3,L1CSR2
        oris    r3,r3,(L1CSR2_DCWS)@h
        mtspr   L1CSR2,r3
@@ -346,6 +379,15 @@ __bootpg_addr:
 __spin_table:
        .space CONFIG_MAX_CPUS*ENTRY_SIZE
 
+       /*
+        * This variable is set by cpu_init_r() after parsing hwconfig
+        * to enable workaround for erratum NMG_CPU_A011.
+        */
+       .align L1_CACHE_SHIFT
+       .global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+       .long   1
+
        /* Fill in the empty space.  The actual reset vector is
         * the last word of the page */
 __secondary_start_code_end: