powerpc/fsl-corenet: work around erratum A004510

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / release.S

diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 53cefaf002e32c2b22d6913cd7c64019bf427fc0..043d0ff773719313cf197252efba9190abc711fd 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  * Kumar Gala <kumar.gala@freescale.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,6 +21,7 @@
  * MA 02111-1307 USA
  */
 
+#include <asm-offsets.h>
 #include <config.h>
 #include <mpc85xx.h>
 #include <version.h>
@@ -67,6 +68,39 @@ __secondary_start_page:
        mtspr   SPRN_HID1,r3
 #endif
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_CPU_A003999
+       mfspr   r3,977
+       oris    r3,r3,0x0100
+       mtspr   977,r3
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
+       mfspr   r3,SPRN_SVR
+       rlwinm  r3,r3,0,0xff
+       li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
+       cmpw    r3,r4
+       beq     1f
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
+       li      r4,CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2
+       cmpw    r3,r4
+       beq     1f
+#endif
+
+       /* Not a supported revision affected by erratum */
+       b       2f
+
+1:     /* Erratum says set bits 55:60 to 001001 */
+       msync
+       isync
+       mfspr   r3,976
+       li      r4,0x48
+       rlwimi  r3,r4,0,0x1f8
+       mtspr   976,r3
+       isync
+2:
+#endif
+
        /* Enable branch prediction */
        lis     r3,BUCSR_ENABLE@h
        ori     r3,r3,BUCSR_ENABLE@l
@@ -136,13 +170,48 @@ __secondary_start_page:
        mtspr   L1CSR2,r8
 #endif
 
-#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
-       mfspr   r8,L1CSR2
-       oris    r8,r8,(L1CSR2_DCWS)@h
-       mtspr   L1CSR2,r8
+#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
+       defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
+       /*
+        * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
+        * also appleis to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
+        */
+       mfspr   r3,SPRN_SVR
+       rlwinm  r6,r3,24,~0x800         /* clear E bit */
+
+       lis     r5,SVR_P4080@h
+       ori     r5,r5,SVR_P4080@l
+       cmpw    r6,r5
+       bne     1f
+
+       rlwinm  r3,r3,0,0xf0
+       li      r5,0x30
+       cmpw    r3,r5
+       bge     2f
+1:
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
+       lis     r3,toreset(enable_cpu_a011_workaround)@ha
+       lwz     r3,toreset(enable_cpu_a011_workaround)@l(r3)
+       cmpwi   r3,0
+       beq     2f
+#endif
+       mfspr   r3,L1CSR2
+       oris    r3,r3,(L1CSR2_DCWS)@h
+       mtspr   L1CSR2,r3
+2:
 #endif
 
 #ifdef CONFIG_BACKSIDE_L2_CACHE
+       /* skip L2 setup on P2040/P2040E as they have no L2 */
+       mfspr   r3,SPRN_SVR
+       rlwinm  r6,r3,24,~0x800         /* clear E bit of SVR */
+
+       lis     r3,SVR_P2040@h
+       ori     r3,r3,SVR_P2040@l
+       cmpw    r6,r3
+       beq 3f
+
        /* Enable/invalidate the L2 cache */
        msync
        lis     r2,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
@@ -168,6 +237,7 @@ __secondary_start_page:
        andis.  r1,r3,L2CSR0_L2E@h
        beq     2b
 #endif
+3:
 
 #define EPAPR_MAGIC            (0x45504150)
 #define ENTRY_ADDR_UPPER       0
@@ -309,6 +379,15 @@ __bootpg_addr:
 __spin_table:
        .space CONFIG_MAX_CPUS*ENTRY_SIZE
 
+       /*
+        * This variable is set by cpu_init_r() after parsing hwconfig
+        * to enable workaround for erratum NMG_CPU_A011.
+        */
+       .align L1_CACHE_SHIFT
+       .global enable_cpu_a011_workaround
+enable_cpu_a011_workaround:
+       .long   1
+
        /* Fill in the empty space.  The actual reset vector is
         * the last word of the page */
 __secondary_start_code_end: