Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

[karo-tx-uboot.git] / arch / powerpc / cpu / mpc85xx / speed.c

diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index f07a28b46217dbed83090a9c1ba824ed770fe014..f00b1abe63f1f78d5c60b3f1300fad5919b09ada 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -82,7 +82,11 @@ void get_sys_info (sys_info_t * sysInfo)
        uint mem_pll_rat;
 
        sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+       sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
        sysInfo->freqDDRBus = sysclk;
+#endif
 
        sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
        mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
@@ -128,10 +132,15 @@ void get_sys_info (sys_info_t * sysInfo)
                sysInfo->freqProcessor[cpu] =
                         freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
        }
+#ifdef CONFIG_PPC_B4860
+#define FM1_CLK_SEL    0xe0000000
+#define FM1_CLK_SHIFT  29
+#else
 #define PME_CLK_SEL    0xe0000000
 #define PME_CLK_SHIFT  29
 #define FM1_CLK_SEL    0x1c000000
 #define FM1_CLK_SHIFT  26
+#endif
        rcw_tmp = in_be32(&gur->rcwsr[7]);
 
 #ifdef CONFIG_SYS_DPAA_PME
@@ -163,6 +172,10 @@ void get_sys_info (sys_info_t * sysInfo)
        }
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
 #ifdef CONFIG_SYS_DPAA_FMAN
        switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
        case 1:
@@ -177,6 +190,9 @@ void get_sys_info (sys_info_t * sysInfo)
        case 4:
                sysInfo->freqFMan[0] = freqCC_PLL[3] / 4;
                break;
+       case 5:
+               sysInfo->freqFMan[0] = sysInfo->freqSystemBus;
+               break;
        case 6:
                sysInfo->freqFMan[0] = freqCC_PLL[4] / 2;
                break;
@@ -277,6 +293,10 @@ void get_sys_info (sys_info_t * sysInfo)
 #endif
 #endif
 
+#ifdef CONFIG_SYS_DPAA_QBMAN
+       sysInfo->freqQMAN = sysInfo->freqSystemBus / 2;
+#endif
+
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 
 #else /* CONFIG_FSL_CORENET */
@@ -383,11 +403,11 @@ int get_clocks (void)
        gd->cpu_clk = sys_info.freqProcessor[0];
        gd->bus_clk = sys_info.freqSystemBus;
        gd->mem_clk = sys_info.freqDDRBus;
-       gd->lbc_clk = sys_info.freqLocalBus;
+       gd->arch.lbc_clk = sys_info.freqLocalBus;
 
 #ifdef CONFIG_QE
-       gd->qe_clk = sys_info.freqQE;
-       gd->brg_clk = gd->qe_clk / 2;
+       gd->arch.qe_clk = sys_info.freqQE;
+       gd->arch.brg_clk = gd->arch.qe_clk / 2;
 #endif
        /*
         * The base clock for I2C depends on the actual SOC.  Unfortunately,
@@ -398,7 +418,7 @@ int get_clocks (void)
         */
 #if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
        defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
-       gd->i2c1_clk = sys_info.freqSystemBus;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus;
 #elif defined(CONFIG_MPC8544)
        /*
         * On the 8544, the I2C clock is the same as the SEC clock.  This can be
@@ -408,29 +428,29 @@ int get_clocks (void)
         * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
         */
        if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
-               gd->i2c1_clk = sys_info.freqSystemBus / 3;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 3;
        else
-               gd->i2c1_clk = sys_info.freqSystemBus / 2;
+               gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #else
        /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
-       gd->i2c1_clk = sys_info.freqSystemBus / 2;
+       gd->arch.i2c1_clk = sys_info.freqSystemBus / 2;
 #endif
-       gd->i2c2_clk = gd->i2c1_clk;
+       gd->arch.i2c2_clk = gd->arch.i2c1_clk;
 
 #if defined(CONFIG_FSL_ESDHC)
 #if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
        defined(CONFIG_P1014)
-       gd->sdhc_clk = gd->bus_clk;
+       gd->arch.sdhc_clk = gd->bus_clk;
 #else
-       gd->sdhc_clk = gd->bus_clk / 2;
+       gd->arch.sdhc_clk = gd->bus_clk / 2;
 #endif
 #endif /* defined(CONFIG_FSL_ESDHC) */
 
 #if defined(CONFIG_CPM2)
-       gd->vco_out = 2*sys_info.freqSystemBus;
-       gd->cpm_clk = gd->vco_out / 2;
-       gd->scc_clk = gd->vco_out / 4;
-       gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+       gd->arch.vco_out = 2*sys_info.freqSystemBus;
+       gd->arch.cpm_clk = gd->arch.vco_out / 2;
+       gd->arch.scc_clk = gd->arch.vco_out / 4;
+       gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
 #endif
 
        if(gd->cpu_clk != 0) return (0);