u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */
u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */
- u32 DQS_config_offset_count; /* DQS Config Offset Count */
- u32 DQS_config_offset_time; /* DQS Config Offset Time */
+ u32 dqs_config_offset_count; /* DQS Config Offset Count */
+ u32 dqs_config_offset_time; /* DQS Config Offset Time */
u32 DQS_delay_status; /* DQS Delay Status */
u32 res0[0xF];
u32 prioman_config1; /* Priority Manager Configuration */
}
#endif /* __ASSEMBLY__ */
-#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000
-#define CONFIG_SYS_MPC512x_USB_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET)
+#define CONFIG_SYS_MPC512x_USB1_OFFSET 0x4000
+#define CONFIG_SYS_MPC512x_USB1_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB1_OFFSET)
#define IIM_BASE_ADDR (CONFIG_SYS_IMMR + offsetof(immap_t, iim))