QE/U-QE: Add U-QE support

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 9d08321f5d3979d2195cd7dc511b0bdbe89287fe..4bda0f193444b3bbbe9b5d14fd0894e8961d3b22 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1722,6 +1722,9 @@ typedef struct ccsr_gur {
        u32     rstrqpblsr;     /* Reset request preboot loader status */
        u8      res11[8];
        u32     rstrqmr1;       /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
+#endif
        u8      res12[4];
        u32     rstrqsr1;       /* Reset request status */
        u8      res13[4];
@@ -1770,6 +1773,10 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL      0x00000080
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH    0x00000000
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT    0x80000000
+#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET    0x28
+#define PXCKEN_MASK    0x80000000
+#define PXCK_MASK      0x00FF0000
+#define PXCK_BITS_START        16
 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
@@ -1882,7 +1889,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
        u32     sata2liodnr;    /* SATA 2 LIODN */
        u32     sata3liodnr;    /* SATA 3 LIODN */
        u32     sata4liodnr;    /* SATA 4 LIODN */
-       u8      res22[32];
+       u8      res22[24];
+       u32     qeliodnr;       /* QE LIODN */
+       u8      res_57c[4];
        u32     dma1liodnr;     /* DMA 1 LIODN */
        u32     dma2liodnr;     /* DMA 2 LIODN */
        u32     dma3liodnr;     /* DMA 3 LIODN */
@@ -2492,6 +2501,7 @@ typedef struct serdes_corenet {
 #define SRDS_RSTCTL_SDEN       0x00000020
 #define SRDS_RSTCTL_SDRST_B    0x00000040
 #define SRDS_RSTCTL_PLLRST_B   0x00000080
+#define SRDS_RSTCTL_RSTERR_SHIFT  29
                u32     pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF               0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK      0x70000000
@@ -2501,6 +2511,7 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_RFCK_SEL_150       0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13    0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88    0x50000000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK     0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5                0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75     0x00050000
@@ -2508,9 +2519,22 @@ typedef struct serdes_corenet {
 #define SRDS_PLLCR0_FRATE_SEL_4                0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12     0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3                0x000a0000
+#define SRDS_PLLCR0_DCBIAS_OVRD                0x000000F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT  4
                u32     pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL  0x08000000
-               u32     res_0c; /* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN            0x20000000
+#define SRDS_PLLCR1_BCAP_OVD           0x10000000
+#define SRDS_PLLCR1_PLL_FCAP           0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT     15
+#define SRDS_PLLCR1_PLL_BWSEL          0x08000000
+#define SRDS_PLLCR1_BYP_CAL            0x02000000
+               u32     pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN            0x00800000
+#define SRDS_PLLSR2_BCAP_EN_SHIFT      23
+#define SRDS_PLLSR2_FCAP               0x003F0000
+#define SRDS_PLLSR2_FCAP_SHIFT         16
+#define SRDS_PLLSR2_DCBIAS             0x000F0000
+#define SRDS_PLLSR2_DCBIAS_SHIFT       16
                u32     pllcr3;
                u32     pllcr4;
                u8      res_18[0x20-0x18];
@@ -2845,6 +2869,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET  0xEB000
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
+#define CONFIG_SYS_FSL_SCFG_OFFSET             0xFC000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET         0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET         0x102000
@@ -2854,6 +2879,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0x130000
+#define CONFIG_SYS_MPC85xx_QE_OFFSET           0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET     0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
        && !defined(CONFIG_PPC_B4420)
@@ -2962,6 +2988,10 @@ struct ccsr_pman {
 
 #define CONFIG_SYS_FSL_CPC_ADDR        \
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_ADDR       \
+       (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
+#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR        \
+       (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \