powerpc/mpc85xx: Add T2080/T2081 SoC support

[karo-tx-uboot.git] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 882b0b15eba9d473ca77679203165e5ddbb9fb00..672e8c6650c39ea703d7cd6307c91b381e92e0b4 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1759,6 +1759,12 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL        0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  17
+#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL                0xff000000
+#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT  24
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL                0x00ff0000
+#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT  16
+#define FSL_CORENET_RCWSR6_BOOT_LOC            0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1        0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2        0x00400000
@@ -1821,6 +1827,15 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII       0x00000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII       0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO               0x10000000
+#endif
+#if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
+#define FSL_CORENET_RCWSR13_EC1                        0x60000000 /* bits 417..418 */
+#define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII   0x00000000
+#define FSL_CORENET_RCWSR13_EC1_GPIO           0x40000000
+#define FSL_CORENET_RCWSR13_EC2                        0x18000000 /* bits 419..420 */
+#define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII   0x00000000
+#define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII  0x08000000
+#define FSL_CORENET_RCWSR13_EC2_GPIO           0x10000000
 #endif
        u8      res18[192];
        u32     scratchrw[4];   /* Scratch Read/Write */
@@ -2818,6 +2833,7 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CPC_OFFSET              0x10000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET         0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET         0x101000
+#define CONFIG_SYS_MPC85xx_DMA3_OFFSET         0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET                0x114000