Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...

[karo-tx-linux.git] / arch / powerpc / include / asm / reg.h

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index e5d2e0bc7e032b64890701cdc91d88e18cd665c6..bffd89d27301db29594688225eb83b1033f5d2e2 100644 (file)
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -215,6 +215,7 @@
 #define SPRN_TEXASR    0x82    /* Transaction EXception & Summary */
 #define   TEXASR_FS    __MASK(63-36)   /* Transaction Failure Summary */
 #define SPRN_TEXASRU   0x83    /* ''      ''      ''    Upper 32  */
+#define   TEXASR_FS     __MASK(63-36) /* TEXASR Failure Summary */
 #define SPRN_TFHAR     0x80    /* Transaction Failure Handler Addr */
 #define SPRN_CTRLF     0x088
 #define SPRN_CTRLT     0x098
@@ -224,6 +225,7 @@
 #define   CTRL_TE      0x00c00000      /* thread enable */
 #define   CTRL_RUNLATCH        0x1
 #define SPRN_DAWR      0xB4
+#define SPRN_RPR       0xBA    /* Relative Priority Register */
 #define SPRN_CIABR     0xBB
 #define   CIABR_PRIV           0x3
 #define   CIABR_PRIV_USER      1
@@ -272,8 +274,10 @@
 #define SPRN_HSRR1     0x13B   /* Hypervisor Save/Restore 1 */
 #define SPRN_IC                0x350   /* Virtual Instruction Count */
 #define SPRN_VTB       0x351   /* Virtual Time Base */
+#define SPRN_LDBAR     0x352   /* LD Base Address Register */
 #define SPRN_PMICR     0x354   /* Power Management Idle Control Reg */
 #define SPRN_PMSR      0x355   /* Power Management Status Reg */
+#define SPRN_PMMAR     0x356   /* Power Management Memory Activity Register */
 #define SPRN_PMCR      0x374   /* Power Management Control Register */
 
 /* HFSCR and FSCR bit numbers are the same */
@@ -433,6 +437,12 @@
 #define HID0_BTCD      (1<<1)          /* Branch target cache disable */
 #define HID0_NOPDST    (1<<1)          /* No-op dst, dstt, etc. instr. */
 #define HID0_NOPTI     (1<<0)          /* No-op dcbt and dcbst instr. */
+/* POWER8 HID0 bits */
+#define HID0_POWER8_4LPARMODE  __MASK(61)
+#define HID0_POWER8_2LPARMODE  __MASK(57)
+#define HID0_POWER8_1TO2LPAR   __MASK(52)
+#define HID0_POWER8_1TO4LPAR   __MASK(51)
+#define HID0_POWER8_DYNLPARDIS __MASK(48)
 
 #define SPRN_HID1      0x3F1           /* Hardware Implementation Register 1 */
 #ifdef CONFIG_6xx
@@ -670,18 +680,20 @@
 #define   MMCR0_PROBLEM_DISABLE MMCR0_FCP
 #define   MMCR0_FCM1   0x10000000UL /* freeze counters while MSR mark = 1 */
 #define   MMCR0_FCM0   0x08000000UL /* freeze counters while MSR mark = 0 */
-#define   MMCR0_PMXE   0x04000000UL /* performance monitor exception enable */
-#define   MMCR0_FCECE  0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_PMXE   ASM_CONST(0x04000000) /* perf mon exception enable */
+#define   MMCR0_FCECE  ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
 #define   MMCR0_TBEE   0x00400000UL /* time base exception enable */
 #define   MMCR0_BHRBA  0x00200000UL /* BHRB Access allowed in userspace */
 #define   MMCR0_EBE    0x00100000UL /* Event based branch enable */
 #define   MMCR0_PMCC   0x000c0000UL /* PMC control */
 #define   MMCR0_PMCC_U6        0x00080000UL /* PMC1-6 are R/W by user (PR) */
 #define   MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
-#define   MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
+#define   MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
 #define   MMCR0_TRIGGER        0x00002000UL /* TRIGGER enable */
-#define   MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */
-#define   MMCR0_PMAO   0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
+#define   MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
+/* performance monitor alert has occurred, set to 0 after handling exception */
+#define   MMCR0_PMAO   ASM_CONST(0x00000080)
 #define   MMCR0_SHRFC  0x00000040UL /* SHRre freeze conditions between threads */
 #define   MMCR0_FC56   0x00000010UL /* freeze counters 5 and 6 */
 #define   MMCR0_FCTI   0x00000008UL /* freeze counters in tags inactive mode */