Merge branches 'einj', 'intel_idle', 'misc', 'srat' and 'turbostat-ivb' into release

[mv-sheeva.git] / arch / powerpc / kernel / swsusp_32.S

diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S
index b0754e237438a0c9e3e919c738231c58eb3c5df4..ba4dee3d233fe8ad8aee6fc226c43978f4c6731a 100644 (file)
--- a/arch/powerpc/kernel/swsusp_32.S
+++ b/arch/powerpc/kernel/swsusp_32.S
@@ -143,7 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
 
        /* Disable MSR:DR to make sure we don't take a TLB or
         * hash miss during the copy, as our hash table will
-        * for a while be unuseable. For .text, we assume we are
+        * for a while be unusable. For .text, we assume we are
         * covered by a BAT. This works only for non-G5 at this
         * point. G5 will need a better approach, possibly using
         * a small temporary hash table filled with large mappings,