Merge tag 'acpica-4.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...

[karo-tx-linux.git] / arch / powerpc / platforms / powernv / pci.h

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 6c02ff8dd69f42797ac9443eee6f8a0778ed5175..070ee888fc95cef223337e3bd945726ffc7ac7cc 100644 (file)
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -23,6 +23,7 @@ enum pnv_phb_model {
 #define PNV_IODA_PE_BUS_ALL    (1 << 2)        /* PE has subordinate buses     */
 #define PNV_IODA_PE_MASTER     (1 << 3)        /* Master PE in compound case   */
 #define PNV_IODA_PE_SLAVE      (1 << 4)        /* Slave PE in compound case    */
+#define PNV_IODA_PE_VF         (1 << 5)        /* PE for one VF                */
 
 /* Data associated with a PE, including IOMMU tracking etc.. */
 struct pnv_phb;
@@ -34,6 +35,9 @@ struct pnv_ioda_pe {
         * entire bus (& children). In the former case, pdev
         * is populated, in the later case, pbus is.
         */
+#ifdef CONFIG_PCI_IOV
+       struct pci_dev          *parent_dev;
+#endif
        struct pci_dev          *pdev;
        struct pci_bus          *pbus;
 
@@ -53,7 +57,7 @@ struct pnv_ioda_pe {
        /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
        int                     tce32_seg;
        int                     tce32_segcount;
-       struct iommu_table      tce32_table;
+       struct iommu_table      *tce32_table;
        phys_addr_t             tce_inval_reg_phys;
 
        /* 64-bit TCE bypass region */
@@ -75,22 +79,6 @@ struct pnv_ioda_pe {
        struct list_head        list;
 };
 
-/* IOC dependent EEH operations */
-#ifdef CONFIG_EEH
-struct pnv_eeh_ops {
-       int (*post_init)(struct pci_controller *hose);
-       int (*set_option)(struct eeh_pe *pe, int option);
-       int (*get_state)(struct eeh_pe *pe);
-       int (*reset)(struct eeh_pe *pe, int option);
-       int (*get_log)(struct eeh_pe *pe, int severity,
-                      char *drv_log, unsigned long len);
-       int (*configure_bridge)(struct eeh_pe *pe);
-       int (*err_inject)(struct eeh_pe *pe, int type, int func,
-                         unsigned long addr, unsigned long mask);
-       int (*next_error)(struct eeh_pe **pe);
-};
-#endif /* CONFIG_EEH */
-
 #define PNV_PHB_FLAG_EEH       (1 << 0)
 
 struct pnv_phb {
@@ -104,10 +92,6 @@ struct pnv_phb {
        int                     initialized;
        spinlock_t              lock;
 
-#ifdef CONFIG_EEH
-       struct pnv_eeh_ops      *eeh_ops;
-#endif
-
 #ifdef CONFIG_DEBUG_FS
        int                     has_dbgfs;
        struct dentry           *dbgfs;
@@ -165,6 +149,8 @@ struct pnv_phb {
 
                        /* PE allocation bitmap */
                        unsigned long           *pe_alloc;
+                       /* PE allocation mutex */
+                       struct mutex            pe_alloc_mutex;
 
                        /* M32 & IO segment maps */
                        unsigned int            *m32_segmap;
@@ -179,6 +165,7 @@ struct pnv_phb {
                         * on the sequence of creation
                         */
                        struct list_head        pe_list;
+                       struct mutex            pe_list_mutex;
 
                        /* Reverse map of PEs, will have to extend if
                         * we are to support more than 256 PEs, indexed
@@ -213,15 +200,12 @@ struct pnv_phb {
 };
 
 extern struct pci_ops pnv_pci_ops;
-#ifdef CONFIG_EEH
-extern struct pnv_eeh_ops ioda_eeh_ops;
-#endif
 
 void pnv_pci_dump_phb_diag_data(struct pci_controller *hose,
                                unsigned char *log_buff);
-int pnv_pci_cfg_read(struct device_node *dn,
+int pnv_pci_cfg_read(struct pci_dn *pdn,
                     int where, int size, u32 *val);
-int pnv_pci_cfg_write(struct device_node *dn,
+int pnv_pci_cfg_write(struct pci_dn *pdn,
                      int where, int size, u32 val);
 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                      void *tce_mem, u64 tce_size,
@@ -232,6 +216,6 @@ extern void pnv_pci_init_ioda2_phb(struct device_node *np);
 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
                                        __be64 *startp, __be64 *endp, bool rm);
 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
-extern int ioda_eeh_phb_reset(struct pci_controller *hose, int option);
+extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
 
 #endif /* __POWERNV_PCI_H */