powerpc/powernv/npu: Rework TCE Kill handling

[karo-tx-linux.git] / arch / powerpc / platforms / powernv / pci.h

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 3f814f382b2e793bf0b5374abb74bebf35246a98..2b35606a0a567b9e544f2b8414346b8825461014 100644 (file)
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -24,7 +24,6 @@ enum pnv_phb_model {
 #define PNV_IODA_PE_MASTER     (1 << 3)        /* Master PE in compound case   */
 #define PNV_IODA_PE_SLAVE      (1 << 4)        /* Slave PE in compound case    */
 #define PNV_IODA_PE_VF         (1 << 5)        /* PE for one VF                */
-#define PNV_IODA_PE_PEER       (1 << 6)        /* PE has peers                 */
 
 /* Data associated with a PE, including IOMMU tracking etc.. */
 struct pnv_phb;
@@ -32,9 +31,6 @@ struct pnv_ioda_pe {
        unsigned long           flags;
        struct pnv_phb          *phb;
 
-#define PNV_IODA_MAX_PEER_PES  8
-       struct pnv_ioda_pe      *peers[PNV_IODA_MAX_PEER_PES];
-
        /* A PE can be associated with a single device or an
         * entire bus (& children). In the former case, pdev
         * is populated, in the later case, pbus is.
@@ -53,14 +49,7 @@ struct pnv_ioda_pe {
        /* PE number */
        unsigned int            pe_number;
 
-       /* "Weight" assigned to the PE for the sake of DMA resource
-        * allocations
-        */
-       unsigned int            dma_weight;
-
        /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
-       int                     tce32_seg;
-       int                     tce32_segcount;
        struct iommu_table_group table_group;
 
        /* 64-bit TCE bypass region */
@@ -78,7 +67,6 @@ struct pnv_ioda_pe {
        struct list_head        slaves;
 
        /* Link in list of PE#s */
-       struct list_head        dma_link;
        struct list_head        list;
 };
 
@@ -110,19 +98,18 @@ struct pnv_phb {
                         unsigned int is_64, struct msi_msg *msg);
        void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
        void (*fixup_phb)(struct pci_controller *hose);
-       u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
        int (*init_m64)(struct pnv_phb *phb);
        void (*reserve_m64_pe)(struct pci_bus *bus,
                               unsigned long *pe_bitmap, bool all);
-       int (*pick_m64_pe)(struct pci_bus *bus, bool all);
+       struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
        int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
        void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
        int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
 
        struct {
                /* Global bridge info */
-               unsigned int            total_pe;
-               unsigned int            reserved_pe;
+               unsigned int            total_pe_num;
+               unsigned int            reserved_pe_idx;
 
                /* 32-bit MMIO window */
                unsigned int            m32_size;
@@ -141,15 +128,19 @@ struct pnv_phb {
                unsigned int            io_segsize;
                unsigned int            io_pci_base;
 
-               /* PE allocation bitmap */
-               unsigned long           *pe_alloc;
-               /* PE allocation mutex */
+               /* PE allocation */
                struct mutex            pe_alloc_mutex;
+               unsigned long           *pe_alloc;
+               struct pnv_ioda_pe      *pe_array;
 
                /* M32 & IO segment maps */
+               unsigned int            *m64_segmap;
                unsigned int            *m32_segmap;
                unsigned int            *io_segmap;
-               struct pnv_ioda_pe      *pe_array;
+
+               /* DMA32 segment maps - IODA1 only */
+               unsigned int            dma32_count;
+               unsigned int            *dma32_segmap;
 
                /* IRQ chip */
                int                     irq_chip_init;
@@ -167,20 +158,6 @@ struct pnv_phb {
                 */
                unsigned char           pe_rmap[0x10000];
 
-               /* 32-bit TCE tables allocation */
-               unsigned long           tce32_count;
-
-               /* Total "weight" for the sake of DMA resources
-                * allocation
-                */
-               unsigned int            dma_weight;
-               unsigned int            dma_pe_count;
-
-               /* Sorted list of used PE's, sorted at
-                * boot for resource allocation purposes
-                */
-               struct list_head        pe_dma_list;
-
                /* TCE cache invalidate registers (physical and
                 * remapped)
                 */
@@ -236,16 +213,17 @@ extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
 extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
 extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
 
+extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
+                           const char *fmt, ...);
+#define pe_err(pe, fmt, ...)                                   \
+       pe_level_printk(pe, KERN_ERR, fmt, ##__VA_ARGS__)
+#define pe_warn(pe, fmt, ...)                                  \
+       pe_level_printk(pe, KERN_WARNING, fmt, ##__VA_ARGS__)
+#define pe_info(pe, fmt, ...)                                  \
+       pe_level_printk(pe, KERN_INFO, fmt, ##__VA_ARGS__)
+
 /* Nvlink functions */
-extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe *npe);
-extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe *npe,
-                                      struct iommu_table *tbl,
-                                      unsigned long index,
-                                      unsigned long npages,
-                                      bool rm);
-extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe *npe);
-extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe *npe);
-extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe *npe, bool enabled);
-extern int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask);
+extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
+extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
 
 #endif /* __POWERNV_PCI_H */