powerpc/powernv: Introduce address translation services for Nvlink2

[karo-tx-linux.git] / arch / powerpc / platforms / powernv / pci.h

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index e1d3e5526b548fae3bf67f7843159c780b351cef..4eab713136d16e53eff2b74d8b2bedafb92b0c08 100644 (file)
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -7,6 +7,9 @@
 
 struct pci_dn;
 
+/* Maximum possible number of ATSD MMIO registers per NPU */
+#define NV_NMMU_ATSD_REGS 8
+
 enum pnv_phb_type {
        PNV_PHB_IODA1   = 0,
        PNV_PHB_IODA2   = 1,
@@ -174,6 +177,16 @@ struct pnv_phb {
                struct OpalIoP7IOCErrorData     hub_diag;
        } diag;
 
+       /* Nvlink2 data */
+       struct npu {
+               int index;
+               __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
+               unsigned int mmio_atsd_count;
+
+               /* Bitmask for MMIO register usage */
+               unsigned long mmio_atsd_usage;
+       } npu;
+
 #ifdef CONFIG_CXL_BASE
        struct cxl_afu *cxl_afu;
 #endif
@@ -236,7 +249,7 @@ extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
 extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
 extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
 extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
-
+extern int pnv_npu2_init(struct pnv_phb *phb);
 
 /* cxl functions */
 extern bool pnv_cxl_enable_device_hook(struct pci_dev *dev);