[POWERPC] 85xx: Don't write reserved values to MAS1[TSIZE]

[mv-sheeva.git] / arch / ppc / kernel / head_fsl_booke.S

diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S
index 8d60fa99fc4b992a402ec73dfa516b139f049d08..54f40d95cdb99e87aa417058a1e0d96d0f824838 100644 (file)
--- a/arch/ppc/kernel/head_fsl_booke.S
+++ b/arch/ppc/kernel/head_fsl_booke.S
@@ -1,6 +1,4 @@
 /*
- * arch/ppc/kernel/head_fsl_booke.S
- *
  * Kernel execution entry point code.
  *
  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
@@ -32,7 +30,6 @@
  * option) any later version.
  */
 
-#include <linux/config.h>
 #include <linux/threads.h>
 #include <asm/processor.h>
 #include <asm/page.h>
@@ -209,7 +206,8 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        rlwimi  r7,r3,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r3) */
        mtspr   SPRN_MAS0,r7
        tlbre
-       li      r6,0
+       mfspr   r6,SPRN_MAS1
+       rlwinm  r6,r6,0,2,0     /* clear IPROT */
        mtspr   SPRN_MAS1,r6
        tlbwe
        /* Invalidate TLB1 */
@@ -251,6 +249,8 @@ skpinv:     addi    r6,r6,1                         /* Increment */
        rlwimi  r7,r5,16,4,15   /* Setup MAS0 = TLBSEL | ESEL(r5) */
        mtspr   SPRN_MAS0,r7
        tlbre
+       mfspr   r8,SPRN_MAS1
+       rlwinm  r8,r8,0,2,0     /* clear IPROT */
        mtspr   SPRN_MAS1,r8
        tlbwe
        /* Invalidate TLB1 */
@@ -316,6 +316,7 @@ skpinv:     addi    r6,r6,1                         /* Increment */
         */
        lis     r2,DBCR0_IDM@h
        mtspr   SPRN_DBCR0,r2
+       isync
        /* clear any residual debug events */
        li      r2,-1
        mtspr   SPRN_DBSR,r2
@@ -1002,12 +1003,15 @@ _GLOBAL(giveup_fpu)
 _GLOBAL(abort)
        li      r13,0
         mtspr   SPRN_DBCR0,r13         /* disable all debug events */
+       isync
        mfmsr   r13
        ori     r13,r13,MSR_DE@l        /* Enable Debug Events */
        mtmsr   r13
+       isync
         mfspr   r13,SPRN_DBCR0
         lis    r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
         mtspr   SPRN_DBCR0,r13
+       isync
 
 _GLOBAL(set_context)