Merge master.kernel.org:/home/rmk/linux-2.6-arm

[mv-sheeva.git] / arch / ppc / syslib / open_pic.c

diff --git a/arch/ppc/syslib/open_pic.c b/arch/ppc/syslib/open_pic.c
index 9d4ed68b580419c5c7e1e0e02509a58e9e29ca60..53da58523e39f3380e303f4f33e0ca20c32db81d 100644 (file)
--- a/arch/ppc/syslib/open_pic.c
+++ b/arch/ppc/syslib/open_pic.c
@@ -21,7 +21,6 @@
 #include <asm/signal.h>
 #include <asm/io.h>
 #include <asm/irq.h>
-#include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/open_pic.h>
 #include <asm/i8259.h>
@@ -275,7 +274,7 @@ static void __init openpic_enable_sie(void)
 }
 #endif
 
-#if defined(CONFIG_EPIC_SERIAL_MODE) || defined(CONFIG_PM)
+#if defined(CONFIG_EPIC_SERIAL_MODE)
 static void openpic_reset(void)
 {
        openpic_setfield(&OpenPIC->Global.Global_Configuration0,
@@ -371,8 +370,9 @@ void __init openpic_init(int offset)
        /* Initialize IPI interrupts */
        if ( ppc_md.progress ) ppc_md.progress("openpic: ipi",0x3bb);
        for (i = 0; i < OPENPIC_NUM_IPI; i++) {
-               /* Disabled, Priority 10..13 */
-               openpic_initipi(i, 10+i, OPENPIC_VEC_IPI+i+offset);
+               /* Disabled, increased priorities 10..13 */
+               openpic_initipi(i, OPENPIC_PRIORITY_IPI_BASE+i,
+                               OPENPIC_VEC_IPI+i+offset);
                /* IPIs are per-CPU */
                irq_desc[OPENPIC_VEC_IPI+i+offset].status |= IRQ_PER_CPU;
                irq_desc[OPENPIC_VEC_IPI+i+offset].handler = &open_pic_ipi;
@@ -400,8 +400,9 @@ void __init openpic_init(int offset)
                if (sense & IRQ_SENSE_MASK)
                        irq_desc[i+offset].status = IRQ_LEVEL;
 
-               /* Enabled, Priority 8 */
-               openpic_initirq(i, 8, i+offset, (sense & IRQ_POLARITY_MASK),
+               /* Enabled, Default priority */
+               openpic_initirq(i, OPENPIC_PRIORITY_DEFAULT, i+offset,
+                               (sense & IRQ_POLARITY_MASK),
                                (sense & IRQ_SENSE_MASK));
                /* Processor 0 */
                openpic_mapirq(i, CPU_MASK_CPU0, CPU_MASK_NONE);
@@ -656,6 +657,18 @@ static void __init openpic_maptimer(u_int timer, cpumask_t cpumask)
                      cpus_addr(phys)[0]);
 }
 
+/*
+ * Change the priority of an interrupt
+ */
+void __init
+openpic_set_irq_priority(u_int irq, u_int pri)
+{
+       check_arg_irq(irq);
+       openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
+                               OPENPIC_PRIORITY_MASK,
+                               pri << OPENPIC_PRIORITY_SHIFT);
+}
+
 /*
  * Initalize the interrupt source which will generate an NMI.
  * This raises the interrupt's priority from 8 to 9.
@@ -666,9 +679,7 @@ void __init
 openpic_init_nmi_irq(u_int irq)
 {
        check_arg_irq(irq);
-       openpic_safe_writefield(&ISR[irq - open_pic_irq_offset]->Vector_Priority,
-                               OPENPIC_PRIORITY_MASK,
-                               9 << OPENPIC_PRIORITY_SHIFT);
+       openpic_set_irq_priority(irq, OPENPIC_PRIORITY_NMI);
 }
 
 /*
@@ -937,7 +948,7 @@ static void openpic_cached_disable_irq(u_int irq)
  * we need something better to deal with that... Maybe switch to S1 for
  * cpufreq changes
  */
-int openpic_suspend(struct sys_device *sysdev, u32 state)
+int openpic_suspend(struct sys_device *sysdev, pm_message_t state)
 {
        int     i;
        unsigned long flags;
@@ -993,8 +1004,6 @@ int openpic_resume(struct sys_device *sysdev)
                return 0;
        }
 
-       openpic_reset();
-
        /* OpenPIC sometimes seem to need some time to be fully back up... */
        do {
                openpic_set_spurious(OPENPIC_VEC_SPURIOUS);