Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[mv-sheeva.git] / arch / sh / mm / flush-sh4.c

diff --git a/arch/sh/mm/flush-sh4.c b/arch/sh/mm/flush-sh4.c
index edefc53891a821b0e20db68c95f6ed66c71f06df..cef402678f42b77728b749530387ce8f45267d50 100644 (file)
--- a/arch/sh/mm/flush-sh4.c
+++ b/arch/sh/mm/flush-sh4.c
@@ -8,38 +8,30 @@
  * START: Virtual Address (U0, P1, or P3)
  * SIZE: Size of the region.
  */
-void __weak __flush_wback_region(void *start, int size)
+static void sh4__flush_wback_region(void *start, int size)
 {
-       unsigned long v, cnt, end;
+       reg_size_t aligned_start, v, cnt, end;
 
-       v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
-       end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+       aligned_start = register_align(start);
+       v = aligned_start & ~(L1_CACHE_BYTES-1);
+       end = (aligned_start + size + L1_CACHE_BYTES-1)
                & ~(L1_CACHE_BYTES-1);
        cnt = (end - v) / L1_CACHE_BYTES;
 
        while (cnt >= 8) {
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
                cnt -= 8;
        }
 
        while (cnt) {
-               asm volatile("ocbwb     @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbwb(v); v += L1_CACHE_BYTES;
                cnt--;
        }
 }
@@ -50,37 +42,29 @@ void __weak __flush_wback_region(void *start, int size)
  * START: Virtual Address (U0, P1, or P3)
  * SIZE: Size of the region.
  */
-void __weak __flush_purge_region(void *start, int size)
+static void sh4__flush_purge_region(void *start, int size)
 {
-       unsigned long v, cnt, end;
+       reg_size_t aligned_start, v, cnt, end;
 
-       v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
-       end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+       aligned_start = register_align(start);
+       v = aligned_start & ~(L1_CACHE_BYTES-1);
+       end = (aligned_start + size + L1_CACHE_BYTES-1)
                & ~(L1_CACHE_BYTES-1);
        cnt = (end - v) / L1_CACHE_BYTES;
 
        while (cnt >= 8) {
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
                cnt -= 8;
        }
        while (cnt) {
-               asm volatile("ocbp      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbp(v); v += L1_CACHE_BYTES;
                cnt--;
        }
 }
@@ -88,38 +72,37 @@ void __weak __flush_purge_region(void *start, int size)
 /*
  * No write back please
  */
-void __weak __flush_invalidate_region(void *start, int size)
+static void sh4__flush_invalidate_region(void *start, int size)
 {
-       unsigned long v, cnt, end;
+       reg_size_t aligned_start, v, cnt, end;
 
-       v = (unsigned long)start & ~(L1_CACHE_BYTES-1);
-       end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
+       aligned_start = register_align(start);
+       v = aligned_start & ~(L1_CACHE_BYTES-1);
+       end = (aligned_start + size + L1_CACHE_BYTES-1)
                & ~(L1_CACHE_BYTES-1);
        cnt = (end - v) / L1_CACHE_BYTES;
 
        while (cnt >= 8) {
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
                cnt -= 8;
        }
 
        while (cnt) {
-               asm volatile("ocbi      @%0" : : "r" (v));
-               v += L1_CACHE_BYTES;
+               __ocbi(v); v += L1_CACHE_BYTES;
                cnt--;
        }
 }
+
+void __init sh4__flush_region_init(void)
+{
+       __flush_wback_region            = sh4__flush_wback_region;
+       __flush_invalidate_region       = sh4__flush_invalidate_region;
+       __flush_purge_region            = sh4__flush_purge_region;
+}