x86: Emit port 80 post codes in show_boot_progress()

[karo-tx-uboot.git] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 22a643c9d6bc8098200866471c9b784dc5e8b163..5a4c3e5b1c7b6f086c5db85685827c453fcffc4c 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -26,8 +26,12 @@
 #include <asm/u-boot-x86.h>
 #include <flash.h>
 #include <netdev.h>
+#include <asm/msr.h>
+#include <asm/cache.h>
+#include <asm/io.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
+#include <asm/arch/timestamp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,6 +45,9 @@ int cpu_init_f(void)
        int ret = get_coreboot_info(&lib_sysinfo);
        if (ret != 0)
                printf("Failed to parse coreboot tables.\n");
+
+       timestamp_init();
+
        return ret;
 }
 
@@ -62,6 +69,7 @@ int board_early_init_r(void)
 
 void show_boot_progress(int val)
 {
+       outb(val, 0x80);
 }
 
 
@@ -85,3 +93,19 @@ int board_eth_init(bd_t *bis)
 void setup_pcat_compatibility()
 {
 }
+
+#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
+#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
+
+int board_final_cleanup(void)
+{
+       /* Un-cache the ROM so the kernel has one
+        * more MTRR available.
+        */
+       disable_caches();
+       wrmsrl(MTRRphysBase_MSR(7), 0);
+       wrmsrl(MTRRphysMask_MSR(7), 0);
+       enable_caches();
+
+       return 0;
+}