#include <pci.h>
#include <asm/pci.h>
-static struct pci_controller coreboot_hose;
+DECLARE_GLOBAL_DATA_PTR;
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
u8 secondary;
hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
- hose->last_busno = max(hose->last_busno, secondary);
+ hose->last_busno = max(hose->last_busno, (int)secondary);
pci_hose_scan_bus(hose, secondary);
}
{}
};
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
{
- coreboot_hose.config_table = pci_coreboot_config_table;
- coreboot_hose.first_busno = 0;
- coreboot_hose.last_busno = 0;
+ hose->config_table = pci_coreboot_config_table;
+ hose->first_busno = 0;
+ hose->last_busno = 0;
- pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
- PCI_REGION_MEM);
- coreboot_hose.region_count = 1;
+ /* PCI memory space */
+ pci_set_region(hose->regions + 0,
+ CONFIG_PCI_MEM_BUS,
+ CONFIG_PCI_MEM_PHYS,
+ CONFIG_PCI_MEM_SIZE,
+ PCI_REGION_MEM);
- pci_setup_type1(&coreboot_hose);
+ /* PCI IO space */
+ pci_set_region(hose->regions + 1,
+ CONFIG_PCI_IO_BUS,
+ CONFIG_PCI_IO_PHYS,
+ CONFIG_PCI_IO_SIZE,
+ PCI_REGION_IO);
- pci_register_hose(&coreboot_hose);
+ pci_set_region(hose->regions + 2,
+ CONFIG_PCI_PREF_BUS,
+ CONFIG_PCI_PREF_PHYS,
+ CONFIG_PCI_PREF_SIZE,
+ PCI_REGION_PREFETCH);
- pci_hose_scan(&coreboot_hose);
+ pci_set_region(hose->regions + 3,
+ 0,
+ 0,
+ gd->ram_size,
+ PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+
+ hose->region_count = 4;
}