x86: Refactor PIRQ routing support

[karo-tx-uboot.git] / arch / x86 / dts / crownbay.dts

diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index e81054ebc53c091c6cfc66218c420de3f4bd76a2..d68efda8dfd1b81f2473eac3cd3b077dccfa5a7e 100644 (file)
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 
@@ -13,6 +15,10 @@
        model = "Intel Crown Bay";
        compatible = "intel,crownbay", "intel,queensbay";
 
+       aliases {
+               spi0 = "/spi";
+       };
+
        config {
                silent_console = <0>;
        };
@@ -46,7 +52,7 @@
        spi {
                #address-cells = <1>;
                #size-cells = <0>;
-               compatible = "intel,ich7";
+               compatible = "intel,ich-spi";
                spi-flash@0 {
                        reg = <0>;
                        compatible = "sst,25vf016b", "spi-flash";
@@ -131,6 +137,58 @@
                                };
                        };
                };
+
+               irq-router@1f,0 {
+                       reg = <0x0000f800 0 0 0 0>;
+                       compatible = "intel,irq-router";
+                       intel,pirq-config = "pci";
+                       intel,pirq-link = <0x60 8>;
+                       intel,pirq-mask = <0xdee0>;
+                       intel,pirq-routing = <
+                               /* TunnelCreek PCI devices */
+                               PCI_BDF(0, 2, 0) INTA PIRQE
+                               PCI_BDF(0, 3, 0) INTA PIRQF
+                               PCI_BDF(0, 23, 0) INTA PIRQE
+                               PCI_BDF(0, 24, 0) INTA PIRQF
+                               PCI_BDF(0, 25, 0) INTA PIRQG
+                               PCI_BDF(0, 26, 0) INTA PIRQH
+                               PCI_BDF(0, 27, 0) INTA PIRQG
+                               /*
+                                * Topcliff PCI devices
+                                *
+                                * Note on the Crown Bay board, Topcliff chipset
+                                * is connected to TunnelCreek PCIe port 0, so
+                                * its bus number is 1 for its PCIe port and 2
+                                * for its PCI devices per U-Boot currnet PCI
+                                * bus enumeration algorithm.
+                                */
+                               PCI_BDF(1, 0, 0) INTA PIRQA
+                               PCI_BDF(2, 0, 1) INTA PIRQA
+                               PCI_BDF(2, 0, 2) INTA PIRQA
+                               PCI_BDF(2, 2, 0) INTB PIRQB
+                               PCI_BDF(2, 2, 1) INTB PIRQB
+                               PCI_BDF(2, 2, 2) INTB PIRQB
+                               PCI_BDF(2, 2, 3) INTB PIRQB
+                               PCI_BDF(2, 2, 4) INTB PIRQB
+                               PCI_BDF(2, 4, 0) INTC PIRQC
+                               PCI_BDF(2, 4, 1) INTC PIRQC
+                               PCI_BDF(2, 6, 0) INTD PIRQD
+                               PCI_BDF(2, 8, 0) INTA PIRQA
+                               PCI_BDF(2, 8, 1) INTA PIRQA
+                               PCI_BDF(2, 8, 2) INTA PIRQA
+                               PCI_BDF(2, 8, 3) INTA PIRQA
+                               PCI_BDF(2, 10, 0) INTB PIRQB
+                               PCI_BDF(2, 10, 1) INTB PIRQB
+                               PCI_BDF(2, 10, 2) INTB PIRQB
+                               PCI_BDF(2, 10, 3) INTB PIRQB
+                               PCI_BDF(2, 10, 4) INTB PIRQB
+                               PCI_BDF(2, 12, 0) INTC PIRQC
+                               PCI_BDF(2, 12, 1) INTC PIRQC
+                               PCI_BDF(2, 12, 2) INTC PIRQC
+                               PCI_BDF(2, 12, 3) INTC PIRQC
+                               PCI_BDF(2, 12, 4) INTC PIRQC
+                       >;
+               };
        };
 
 };