Merge branch 'utilities' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux

[karo-tx-linux.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6da2b30781ff7f416c03a2c1584b2e43f90247c8..d8638e2419cc922208357b133e432dff09fb0916 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -45,8 +45,10 @@
 #define MSR_IA32_PERFCTR1              0x000000c2
 #define MSR_FSB_FREQ                   0x000000cd
 #define MSR_PLATFORM_INFO              0x000000ce
+#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT      31
+#define MSR_PLATFORM_INFO_CPUID_FAULT          BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
 
-#define MSR_NHM_SNB_PKG_CST_CFG_CTL    0x000000e2
+#define MSR_PKG_CST_CONFIG_CONTROL     0x000000e2
 #define NHM_C3_AUTO_DEMOTE             (1UL << 25)
 #define NHM_C1_AUTO_DEMOTE             (1UL << 26)
 #define ATM_LNC_C6_AUTO_DEMOTE         (1UL << 25)
@@ -127,6 +129,7 @@
 
 /* DEBUGCTLMSR bits (others vary by model): */
 #define DEBUGCTLMSR_LBR                        (1UL <<  0) /* last branch recording */
+#define DEBUGCTLMSR_BTF_SHIFT          1
 #define DEBUGCTLMSR_BTF                        (1UL <<  1) /* single-step on branches */
 #define DEBUGCTLMSR_TR                 (1UL <<  6)
 #define DEBUGCTLMSR_BTS                        (1UL <<  7)
@@ -147,6 +150,7 @@
 /* C-state Residency Counters */
 #define MSR_PKG_C3_RESIDENCY           0x000003f8
 #define MSR_PKG_C6_RESIDENCY           0x000003f9
+#define MSR_ATOM_PKG_C6_RESIDENCY      0x000003fa
 #define MSR_PKG_C7_RESIDENCY           0x000003fa
 #define MSR_CORE_C3_RESIDENCY          0x000003fc
 #define MSR_CORE_C6_RESIDENCY          0x000003fd
@@ -203,10 +207,17 @@
 #define MSR_PKG_BOTH_CORE_GFXE_C0_RES  0x0000065B
 
 #define MSR_CORE_C1_RES                        0x00000660
+#define MSR_MODULE_C6_RES_MS           0x00000664
 
 #define MSR_CC6_DEMOTION_POLICY_CONFIG 0x00000668
 #define MSR_MC6_DEMOTION_POLICY_CONFIG 0x00000669
 
+#define MSR_ATOM_CORE_RATIOS           0x0000066a
+#define MSR_ATOM_CORE_VIDS             0x0000066b
+#define MSR_ATOM_CORE_TURBO_RATIOS     0x0000066c
+#define MSR_ATOM_CORE_TURBO_VIDS       0x0000066d
+
+
 #define MSR_CORE_PERF_LIMIT_REASONS    0x00000690
 #define MSR_GFX_PERF_LIMIT_REASONS     0x000006B0
 #define MSR_RING_PERF_LIMIT_REASONS    0x000006B1
@@ -463,6 +474,7 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET    0x000001a2
 
+#define MSR_MISC_FEATURE_CONTROL       0x000001a4
 #define MSR_MISC_PWR_MGMT              0x000001aa
 
 #define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
@@ -549,6 +561,13 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT       39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE           (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
+/* MISC_FEATURES_ENABLES non-architectural features */
+#define MSR_MISC_FEATURES_ENABLES      0x00000140
+
+#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT      0
+#define MSR_MISC_FEATURES_ENABLES_CPUID_FAULT          BIT_ULL(MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT)
+#define MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT       1
+
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
 
 /* P4/Xeon+ specific */