Merge branch 'x86-uv-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[karo-tx-linux.git] / arch / x86 / include / asm / uv / uv_mmrs.h

diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index e42249bcf7e1068ffa0d0f58e3450dd55cf2a9f1..ddd8db6b6e70c9e44065410d81710867ded2e156 100644 (file)
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -5,7 +5,7 @@
  *
  * SGI UV MMR definitions
  *
- * Copyright (C) 2007-2013 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
  */
 
 #ifndef _ASM_X86_UV_UV_MMRS_H
@@ -2802,6 +2802,46 @@ union uv1h_lb_target_physical_apic_id_mask_u {
        } s1;
 };
 
+/* ========================================================================= */
+/*                          UV3H_GR0_GAM_GR_CONFIG                           */
+/* ========================================================================= */
+#define UV3H_GR0_GAM_GR_CONFIG                         0xc00028UL
+
+#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT              0
+#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT           10
+#define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK              0x000000000000003fUL
+#define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK           0x0000000000000400UL
+
+union uv3h_gr0_gam_gr_config_u {
+       unsigned long   v;
+       struct uv3h_gr0_gam_gr_config_s {
+               unsigned long   m_skt:6;                        /* RW */
+               unsigned long   undef_6_9:4;                    /* Undefined */
+               unsigned long   subspace:1;                     /* RW */
+               unsigned long   reserved:53;
+       } s3;
+};
+
+/* ========================================================================= */
+/*                          UV3H_GR1_GAM_GR_CONFIG                           */
+/* ========================================================================= */
+#define UV3H_GR1_GAM_GR_CONFIG                         0x1000028UL
+
+#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT              0
+#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT           10
+#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK              0x000000000000003fUL
+#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK           0x0000000000000400UL
+
+union uv3h_gr1_gam_gr_config_u {
+       unsigned long   v;
+       struct uv3h_gr1_gam_gr_config_s {
+               unsigned long   m_skt:6;                        /* RW */
+               unsigned long   undef_6_9:4;                    /* Undefined */
+               unsigned long   subspace:1;                     /* RW */
+               unsigned long   reserved:53;
+       } s3;
+};
+
 /* ========================================================================= */
 /*                   UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR                   */
 /* ========================================================================= */