Merge branch 'for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/signal...

[karo-tx-linux.git] / arch / x86 / kernel / apic / apic.c

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 11544d8f1e975e30c1e3c0d9aafa58b4ba67a1da..3722179a49db6d95aa5e868622637e983da44d3c 100644 (file)
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -35,6 +35,7 @@
 #include <linux/smp.h>
 #include <linux/mm.h>
 
+#include <asm/irq_remapping.h>
 #include <asm/perf_event.h>
 #include <asm/x86_init.h>
 #include <asm/pgalloc.h>
@@ -1441,8 +1442,8 @@ void __init bsp_end_local_APIC_setup(void)
         * Now that local APIC setup is completed for BP, configure the fault
         * handling for interrupt remapping.
         */
-       if (intr_remapping_enabled)
-               enable_drhd_fault_handling();
+       if (irq_remapping_enabled)
+               irq_remap_enable_fault_handling();
 
 }
 
@@ -1517,7 +1518,7 @@ void enable_x2apic(void)
 int __init enable_IR(void)
 {
 #ifdef CONFIG_IRQ_REMAP
-       if (!intr_remapping_supported()) {
+       if (!irq_remapping_supported()) {
                pr_debug("intr-remapping not supported\n");
                return -1;
        }
@@ -1528,7 +1529,7 @@ int __init enable_IR(void)
                return -1;
        }
 
-       return enable_intr_remapping();
+       return irq_remapping_enable();
 #endif
        return -1;
 }
@@ -1537,10 +1538,13 @@ void __init enable_IR_x2apic(void)
 {
        unsigned long flags;
        int ret, x2apic_enabled = 0;
-       int dmar_table_init_ret;
+       int hardware_init_ret;
 
-       dmar_table_init_ret = dmar_table_init();
-       if (dmar_table_init_ret && !x2apic_supported())
+       /* Make sure irq_remap_ops are initialized */
+       setup_irq_remapping_ops();
+
+       hardware_init_ret = irq_remapping_prepare();
+       if (hardware_init_ret && !x2apic_supported())
                return;
 
        ret = save_ioapic_entries();
@@ -1556,7 +1560,7 @@ void __init enable_IR_x2apic(void)
        if (x2apic_preenabled && nox2apic)
                disable_x2apic();
 
-       if (dmar_table_init_ret)
+       if (hardware_init_ret)
                ret = -1;
        else
                ret = enable_IR();
@@ -1637,9 +1641,11 @@ static int __init apic_verify(void)
        mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 
        /* The BIOS may have set up the APIC at some other address */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (l & MSR_IA32_APICBASE_ENABLE)
-               mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (l & MSR_IA32_APICBASE_ENABLE)
+                       mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+       }
 
        pr_info("Found and enabled local APIC!\n");
        return 0;
@@ -1657,13 +1663,15 @@ int __init apic_force_enable(unsigned long addr)
         * MSR. This can only be done in software for Intel P6 or later
         * and AMD K7 (Model > 1) or later.
         */
-       rdmsr(MSR_IA32_APICBASE, l, h);
-       if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-               pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
-               enabled_via_apicbase = 1;
+       if (boot_cpu_data.x86 >= 6) {
+               rdmsr(MSR_IA32_APICBASE, l, h);
+               if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                       pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+                       enabled_via_apicbase = 1;
+               }
        }
        return apic_verify();
 }
@@ -2172,8 +2180,8 @@ static int lapic_suspend(void)
        local_irq_save(flags);
        disable_local_APIC();
 
-       if (intr_remapping_enabled)
-               disable_intr_remapping();
+       if (irq_remapping_enabled)
+               irq_remapping_disable();
 
        local_irq_restore(flags);
        return 0;
@@ -2189,7 +2197,7 @@ static void lapic_resume(void)
                return;
 
        local_irq_save(flags);
-       if (intr_remapping_enabled) {
+       if (irq_remapping_enabled) {
                /*
                 * IO-APIC and PIC have their own resume routines.
                 * We just mask them here to make sure the interrupt
@@ -2209,10 +2217,12 @@ static void lapic_resume(void)
                 * FIXME! This will be wrong if we ever support suspend on
                 * SMP! We'll need to do this as part of the CPU restore!
                 */
-               rdmsr(MSR_IA32_APICBASE, l, h);
-               l &= ~MSR_IA32_APICBASE_BASE;
-               l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-               wrmsr(MSR_IA32_APICBASE, l, h);
+               if (boot_cpu_data.x86 >= 6) {
+                       rdmsr(MSR_IA32_APICBASE, l, h);
+                       l &= ~MSR_IA32_APICBASE_BASE;
+                       l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                       wrmsr(MSR_IA32_APICBASE, l, h);
+               }
        }
 
        maxlvt = lapic_get_maxlvt();
@@ -2239,8 +2249,8 @@ static void lapic_resume(void)
        apic_write(APIC_ESR, 0);
        apic_read(APIC_ESR);
 
-       if (intr_remapping_enabled)
-               reenable_intr_remapping(x2apic_mode);
+       if (irq_remapping_enabled)
+               irq_remapping_reenable(x2apic_mode);
 
        local_irq_restore(flags);
 }