x86: apic unification - merge down enable_NMI_through_LVT0

[mv-sheeva.git] / arch / x86 / kernel / apic_32.c

diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
index d6c8983583713d747790587861318a5fb58eb342..01708f128eeee410283dd61e7528d9a6d9195a15 100644 (file)
--- a/arch/x86/kernel/apic_32.c
+++ b/arch/x86/kernel/apic_32.c
@@ -172,11 +172,15 @@ u32 safe_apic_wait_icr_idle(void)
  */
 void __cpuinit enable_NMI_through_LVT0(void)
 {
-       unsigned int v = APIC_DM_NMI;
+       unsigned int v;
+
+       /* unmask and set to NMI */
+       v = APIC_DM_NMI;
 
-       /* Level triggered for 82489DX */
+       /* Level triggered for 82489DX (32bit mode) */
        if (!lapic_is_integrated())
                v |= APIC_LVT_LEVEL_TRIGGER;
+
        apic_write(APIC_LVT0, v);
 }
 
@@ -193,9 +197,13 @@ int get_physical_broadcast(void)
  */
 int lapic_get_maxlvt(void)
 {
-       unsigned int v = apic_read(APIC_LVR);
+       unsigned int v;
 
-       /* 82489DXs do not report # of LVT entries. */
+       v = apic_read(APIC_LVR);
+       /*
+        * - we always have APIC integrated on 64bit mode
+        * - 82489DXs do not report # of LVT entries
+        */
        return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 }