Merge branch 'x86/cpu' into x86/core

[mv-sheeva.git] / arch / x86 / kernel / apic_64.c

diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index cd63c0bc61802a5415a3f8917af5e02bffd459ed..1a6011855af305cd2956f990040c17e9f313653e 100644 (file)
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -97,7 +97,6 @@ static unsigned long apic_phys;
 
 unsigned long mp_lapic_addr;
 
-unsigned int __cpuinitdata maxcpus = NR_CPUS;
 /*
  * Get the LAPIC version
  */
@@ -220,6 +219,11 @@ void __cpuinit enable_NMI_through_LVT0(void)
 
        /* unmask and set to NMI */
        v = APIC_DM_NMI;
+
+       /* Level triggered for 82489DX (32bit mode) */
+       if (!lapic_is_integrated())
+               v |= APIC_LVT_LEVEL_TRIGGER;
+
        apic_write(APIC_LVT0, v);
 }
 
@@ -228,11 +232,14 @@ void __cpuinit enable_NMI_through_LVT0(void)
  */
 int lapic_get_maxlvt(void)
 {
-       unsigned int v, maxlvt;
+       unsigned int v;
 
        v = apic_read(APIC_LVR);
-       maxlvt = GET_APIC_MAXLVT(v);
-       return maxlvt;
+       /*
+        * - we always have APIC integrated on 64bit mode
+        * - 82489DXs do not report # of LVT entries
+        */
+       return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
 }
 
 /*
@@ -1259,12 +1266,6 @@ void __cpuinit generic_processor_info(int apicid, int version)
                return;
        }
 
-       if (num_processors >= maxcpus) {
-               printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
-                      " Processor ignored.\n", maxcpus);
-               return;
-       }
-
        num_processors++;
        cpus_complement(tmp_map, cpu_present_map);
        cpu = first_cpu(tmp_map);