Merge branch 'for-upstream/platform-x86_tpacpi' of git://repo.or.cz/linux-2.6/linux...

[mv-sheeva.git] / arch / x86 / oprofile / op_model_ppro.c

diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 8eb05878554cf382a0cf482947a8ebf7a93fdeeb..5d1727ba409edf7b1bbe2f28d0b38711cd3625fd 100644 (file)
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -37,15 +37,11 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
        for (i = 0; i < num_counters; i++) {
                if (reserve_perfctr_nmi(MSR_P6_PERFCTR0 + i))
                        msrs->counters[i].addr = MSR_P6_PERFCTR0 + i;
-               else
-                       msrs->counters[i].addr = 0;
        }
 
        for (i = 0; i < num_counters; i++) {
                if (reserve_evntsel_nmi(MSR_P6_EVNTSEL0 + i))
                        msrs->controls[i].addr = MSR_P6_EVNTSEL0 + i;
-               else
-                       msrs->controls[i].addr = 0;
        }
 }
 
@@ -57,7 +53,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
        int i;
 
        if (!reset_value) {
-               reset_value = kmalloc(sizeof(reset_value[0]) * num_counters,
+               reset_value = kzalloc(sizeof(reset_value[0]) * num_counters,
                                        GFP_ATOMIC);
                if (!reset_value)
                        return;
@@ -82,9 +78,18 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
 
        /* clear all counters */
        for (i = 0; i < num_counters; ++i) {
-               if (unlikely(!msrs->controls[i].addr))
+               if (unlikely(!msrs->controls[i].addr)) {
+                       if (counter_config[i].enabled && !smp_processor_id())
+                               /*
+                                * counter is reserved, this is on all
+                                * cpus, so report only for cpu #0
+                                */
+                               op_x86_warn_reserved(i);
                        continue;
+               }
                rdmsrl(msrs->controls[i].addr, val);
+               if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
+                       op_x86_warn_in_use(i);
                val &= model->reserved;
                wrmsrl(msrs->controls[i].addr, val);
        }