Merge branch 'warning-cleanup'

[karo-tx-uboot.git] / board / amcc / kilauea / kilauea.c

diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index f30dc8f92411126fd5ae0abb2e22cd55d7ce5870..7e84a61a96da1a3e7d00f3c7de73bc96c8cee3df 100644 (file)
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -36,7 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips   */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 /*
  * Board early initialization function
@@ -197,7 +197,7 @@ int board_early_init_f (void)
                SDR0_CUST0_NDFC_ENABLE |
                SDR0_CUST0_NDFC_BW_8_BIT |
                SDR0_CUST0_NRB_BUSY |
-               (0x80000000 >> (28 + CFG_NAND_CS));
+               (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
        mtsdr(SDR0_CUST0, val);
 
        /*
@@ -210,19 +210,19 @@ int board_early_init_f (void)
        /*
         * Configure FPGA register with PCIe reset
         */
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);    /* assert PCIe reset */
+       out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);     /* assert PCIe reset */
        mdelay(50);
-       out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);    /* deassert PCIe reset */
+       out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7);     /* deassert PCIe reset */
 
        return 0;
 }
 
 int misc_init_r(void)
 {
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
        /* Monitor protection ON by default */
        flash_protect(FLAG_PROTECT_SET,
-                     -CFG_MONITOR_LEN,
+                     -CONFIG_SYS_MONITOR_LEN,
                      0xffffffff,
                      &flash_info[0]);
 #endif
@@ -330,9 +330,9 @@ void pcie_setup_hoses(int busno)
 
                /* setup mem resource */
                pci_set_region(hose->regions + 0,
-                              CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                              CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-                              CFG_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+                              CONFIG_SYS_PCIE_MEMSIZE,
                               PCI_REGION_MEM);
                hose->region_count = 1;
                pci_register_hose(hose);
@@ -374,24 +374,3 @@ int post_hotkeys_pressed(void)
        return 0;       /* No hotkeys supported */
 }
 #endif /* CONFIG_POST */
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-       u32 val[4];
-       int rc;
-
-       ft_cpu_setup(blob, bd);
-
-       /* Fixup NOR mapping */
-       val[0] = 0;                             /* chip select number */
-       val[1] = 0;                             /* always 0 */
-       val[2] = gd->bd->bi_flashstart;
-       val[3] = gd->bd->bi_flashsize;
-       rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
-                                 val, sizeof(val), 1);
-       if (rc)
-               printf("Unable to update property NOR mapping, err=%s\n",
-                      fdt_strerror(rc));
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */