Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / board / amcc / ocotea / ocotea.h

diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h
index 41bd4500d67d1524a631415daf50f6cb380d5961..853002f4b9fd694949ccfb01383fada72ac3a07d 100644 (file)
--- a/board/amcc/ocotea/ocotea.h
+++ b/board/amcc/ocotea/ocotea.h
@@ -2,27 +2,11 @@
  * (C) Copyright 2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /* Board specific FPGA stuff ... */
-#define FPGA_REG0                       (CFG_FPGA_BASE + 0x00)
+#define FPGA_REG0                       (CONFIG_SYS_FPGA_BASE + 0x00)
 #define   FPGA_REG0_SSCG_MASK             0x80
 #define   FPGA_REG0_SSCG_DISABLE          0x00
 #define   FPGA_REG0_SSCG_ENABLE           0x80
@@ -48,7 +32,7 @@
 #define   FPGA_REG0_ONBOARD_FLASH_ENABLE  0x00
 #define   FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
 #define   FPGA_REG0_FLASH                 0x01
-#define FPGA_REG1                       (CFG_FPGA_BASE + 0x01)
+#define FPGA_REG1                       (CONFIG_SYS_FPGA_BASE + 0x01)
 #define   FPGA_REG1_9772_FSELFBX_MASK     0x80
 #define   FPGA_REG1_9772_FSELFBX_6        0x00
 #define   FPGA_REG1_9772_FSELFBX_10       0x80
@@ -71,7 +55,7 @@
 #define   FPGA_REG1_SOURCE_SSDIV1         0x05
 #define   FPGA_REG1_SOURCE_SSDIV2         0x06
 #define   FPGA_REG1_SOURCE_SSDIV4         0x07
-#define FPGA_REG2                       (CFG_FPGA_BASE + 0x02)
+#define FPGA_REG2                       (CONFIG_SYS_FPGA_BASE + 0x02)
 #define   FPGA_REG2_TC0                   0x80
 #define   FPGA_REG2_TC1                   0x40
 #define   FPGA_REG2_TC2                   0x20
@@ -80,8 +64,9 @@
 #define   FPGA_REG2_EXT_INTFACE_MASK      0x04
 #define   FPGA_REG2_EXT_INTFACE_ENABLE    0x00
 #define   FPGA_REG2_EXT_INTFACE_DISABLE   0x04
+#define   FPGA_REG2_SMII_RESET_DISABLE    0x02   /*Use on Ocotea pass 3 boards*/
 #define   FPGA_REG2_DEFAULT_UART1_N       0x01
-#define FPGA_REG3                       (CFG_FPGA_BASE + 0x03)
+#define FPGA_REG3                       (CONFIG_SYS_FPGA_BASE + 0x03)
 #define   FPGA_REG3_GIGABIT_RESET_DISABLE 0x80   /*Use on Ocotea pass 1 boards*/
 #define   FPGA_REG3_ENET_MASK1            0x70   /*Use on Ocotea pass 1 boards*/
 #define   FPGA_REG3_ENET_MASK2            0xF0   /*Use on Ocotea pass 2 boards*/
@@ -107,7 +92,7 @@
 #define   FPGA_REG3_STAT_LED4_DISAB       0x00
 #define   FPGA_REG3_STAT_LED2_DISAB       0x00
 #define   FPGA_REG3_STAT_LED1_DISAB       0x00
-#define FPGA_REG4                       (CFG_FPGA_BASE + 0x04)
+#define FPGA_REG4                       (CONFIG_SYS_FPGA_BASE + 0x04)
 #define   FPGA_REG4_GPHY_MODE10           0x80
 #define   FPGA_REG4_GPHY_MODE100          0x40
 #define   FPGA_REG4_GPHY_MODE1000         0x20