Move arch/ppc to arch/powerpc

[karo-tx-uboot.git] / board / amcc / yucca / yucca.c

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 7315033dc89abd2f69a9a97c96b63f7866d7b8a0..0d23929903ec9051852fe643188e33a83341a226 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -555,7 +555,7 @@ int checkboard (void)
 }
 
 /*
- * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
+ * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with
  * board specific values.
  */
 static int ppc440spe_rev_a(void)
@@ -588,75 +588,6 @@ u32 ddr_clktr(u32 default_val) {
        return default_val;
 }
 
-/*************************************************************************
- *  pci_pre_init
- *
- *  This routine is called just prior to registering the hose and gives
- *  the board the opportunity to check things. Returning a value of zero
- *  indicates that things are bad & PCI initialization should be aborted.
- *
- *     Different boards may wish to customize the pci controller structure
- *     (add regions, override default access routines, etc) or perform
- *     certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
-{
-       unsigned long strap;
-
-       /*-------------------------------------------------------------------+
-        *      The yucca board is always configured as the host & requires the
-        *      PCI arbiter to be enabled.
-        *-------------------------------------------------------------------*/
-       mfsdr(SDR0_SDSTP1, strap);
-       if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
-               printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
-               return 0;
-       }
-
-       return 1;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- *  pci_target_init
- *
- *     The bootstrap configuration provides default settings for the pci
- *     inbound map (PIM). But the bootstrap config choices are limited and
- *     may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
-       /*-------------------------------------------------------------------+
-        * Disable everything
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0SA, 0 ); /* disable */
-       out32r( PCIL0_PIM1SA, 0 ); /* disable */
-       out32r( PCIL0_PIM2SA, 0 ); /* disable */
-       out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
-       /*-------------------------------------------------------------------+
-        * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
-        * strapping options to not support sizes such as 128/256 MB.
-        *-------------------------------------------------------------------*/
-       out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
-       out32r( PCIL0_PIM0LAH, 0 );
-       out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-       out32r( PCIL0_BAR0, 0 );
-
-       /*-------------------------------------------------------------------+
-        * Program the board's subsystem id/vendor id
-        *-------------------------------------------------------------------*/
-       out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
-       out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
-       out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
 #if defined(CONFIG_PCI)
 int board_pcie_card_present(int port)
 {
@@ -678,7 +609,7 @@ int board_pcie_card_present(int port)
 /*
  * For the given slot, set endpoint mode, send power to the slot,
  * turn on the green LED and turn off the yellow LED, enable the
- * clock. In end point mode reset bit is read only.
+ * clock. In endpoint mode reset bit is read only.
  */
 void board_pcie_setup_port(int port, int rootpoint)
 {
@@ -777,17 +708,6 @@ void fpga_init(void)
        return;
 }
 
-#ifdef CONFIG_POST
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
-       return (ctrlc());
-}
-#endif
-
 /*---------------------------------------------------------------------------+
  | onboard_pci_arbiter_selected => from EPLD
  +---------------------------------------------------------------------------*/