Big white-space cleanup.

[karo-tx-uboot.git] / board / amcc / yucca / yucca.c

diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index bb3e59400f0513bb58b334166829b5550e37d10f..11d1743355c7fc7e81ae275f9731a48105b7e4bd 100644 (file)
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -529,10 +529,10 @@ int board_early_init_f (void)
        mtdcr (uic0sr, 0x00000000);     /* clear all interrupts */
        mtdcr (uic0sr, 0xffffffff);     /* clear all interrupts */
 
-       /* SDR0_MFR should be part of Ethernet init */
-       mfsdr (sdr_mfr, mfr);
-       mfr &= ~SDR0_MFR_ECS_MASK;
-       /*mtsdr(sdr_mfr, mfr);*/
+       mfsdr(sdr_mfr, mfr);
+       mfr |= SDR0_MFR_FIXD;           /* Workaround for PCI/DMA */
+       mtsdr(sdr_mfr, mfr);
+
        fpga_init();
 
        return 0;
@@ -737,27 +737,27 @@ void yucca_setup_pcie_fpga_rootpoint(int port)
        case 0:
                rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
                endpoint    = 0;
-               power       = FPGA_REG1A_PE0_PWRON;
+               power       = FPGA_REG1A_PE0_PWRON;
                green_led   = FPGA_REG1A_PE0_GLED;
-               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE0_YLED;
                reset_off   = FPGA_REG1C_PE0_PERST;
                break;
        case 1:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-               power       = FPGA_REG1A_PE1_PWRON;
+               power       = FPGA_REG1A_PE1_PWRON;
                green_led   = FPGA_REG1A_PE1_GLED;
-               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE1_YLED;
                reset_off   = FPGA_REG1C_PE1_PERST;
                break;
        case 2:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-               power       = FPGA_REG1A_PE2_PWRON;
+               power       = FPGA_REG1A_PE2_PWRON;
                green_led   = FPGA_REG1A_PE2_GLED;
-               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE2_YLED;
                reset_off   = FPGA_REG1C_PE2_PERST;
                break;
@@ -794,27 +794,27 @@ void yucca_setup_pcie_fpga_endpoint(int port)
        case 0:
                rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
                endpoint    = 0;
-               power       = FPGA_REG1A_PE0_PWRON;
+               power       = FPGA_REG1A_PE0_PWRON;
                green_led   = FPGA_REG1A_PE0_GLED;
-               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE0_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE0_YLED;
                reset_off   = FPGA_REG1C_PE0_PERST;
                break;
        case 1:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-               power       = FPGA_REG1A_PE1_PWRON;
+               power       = FPGA_REG1A_PE1_PWRON;
                green_led   = FPGA_REG1A_PE1_GLED;
-               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE1_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE1_YLED;
                reset_off   = FPGA_REG1C_PE1_PERST;
                break;
        case 2:
                rootpoint   = 0;
                endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-               power       = FPGA_REG1A_PE2_PWRON;
+               power       = FPGA_REG1A_PE2_PWRON;
                green_led   = FPGA_REG1A_PE2_GLED;
-               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
+               clock       = FPGA_REG1A_PE2_REFCLK_ENABLE;
                yellow_led  = FPGA_REG1A_PE2_YLED;
                reset_off   = FPGA_REG1C_PE2_PERST;
                break;
@@ -853,18 +853,17 @@ void pcie_setup_hoses(int busno)
                        continue;
 
                if (is_end_point(i)) {
-                       printf("PCIE%d: will be configured as endpoint\n",i);
                        yucca_setup_pcie_fpga_endpoint(i);
                        ret = ppc4xx_init_pcie_endport(i);
                } else {
-                       printf("PCIE%d: will be configured as root-complex\n",i);
                        yucca_setup_pcie_fpga_rootpoint(i);
                        ret = ppc4xx_init_pcie_rootport(i);
                }
                if (ret) {
-                       printf("PCIE%d: initialization failed\n", i);
-                       continue;
-               }
+                       printf("PCIE%d: initialization as %s failed\n", i,
+                              is_end_point(i) ? "endpoint" : "root-complex");
+                       continue;
+               }
 
                hose = &pcie_hose[i];
                hose->first_busno = bus;
@@ -885,21 +884,21 @@ void pcie_setup_hoses(int busno)
                        /*
                         * Reson for no scanning is endpoint can not generate
                         * upstream configuration accesses.
-                        */
+                        */
                } else {
                        ppc4xx_setup_pcie_rootpoint(hose, i);
                        env = getenv("pciscandelay");
                        if (env != NULL) {
                                delay = simple_strtoul(env, NULL, 10);
                                if (delay > 5)
-                                       printf("Warning, expect noticable delay before "
+                                       printf("Warning, expect noticable delay before "
                                               "PCIe scan due to 'pciscandelay' value!\n");
                                mdelay(delay * 1000);
                        }
 
                        /*
                         * Config access can only go down stream
-                        */
+                        */
                        hose->last_busno = pci_hose_scan(hose);
                        bus = hose->last_busno + 1;
                }