#include <common.h>
#include <asm/processor.h>
+#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
+/* FPGA internal regs */
+#define FPGA_CTRL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
+#define FPGA_STATUS ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
+#define FPGA_CTR ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
+#define FPGA_BL ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
+
+/* FPGA Control Reg */
+#define FPGA_CTRL_REV0 0x0001
+#define FPGA_CTRL_REV1 0x0002
+#define FPGA_CTRL_VGA0_BL 0x0004
+#define FPGA_CTRL_VGA0_BL_MODE 0x0008
+#define FPGA_CTRL_CF_RESET 0x0040
+#define FPGA_CTRL_PS2_PWR 0x0080
+#define FPGA_CTRL_CF_PWRN 0x0100 /* low active */
+#define FPGA_CTRL_CF_BUS_EN 0x0200
+#define FPGA_CTRL_LCD_CLK 0x7000 /* mask for lcd clock */
+#define FPGA_CTRL_OW_ENABLE 0x8000
+
+#define FPGA_STATUS_CF_DETECT 0x8000
+
#ifdef CONFIG_VIDEO_SM501
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
#define FPGA_DEBUG
#endif
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
extern void lxt971_no_sleep(void);
/* fpga configuration data - gzip compressed and generated by bin2c */
#include "../common/fpga.c"
-/* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-
-
/* logo bitmap data - gzip compressed and generated by bin2c */
unsigned char logo_bmp_320[] =
{
/*
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
*/
- osrh_reg = in32(GPIO0_OSRH);
- isr1h_reg = in32(GPIO0_ISR1H);
- tcr_reg = in32(GPIO0_TCR);
- out32(GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
- out32(GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
- out32(GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
+ osrh_reg = in_be32((void *)GPIO0_OSRH);
+ isr1h_reg = in_be32((void *)GPIO0_ISR1H);
+ tcr_reg = in_be32((void *)GPIO0_TCR);
+ out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000); /* select input */
udelay(1000); /* wait some time before reading input */
- value = in32(GPIO0_IR) & 0x80400000; /* get config bits */
+ value = in_be32((void *)GPIO0_IR) & 0x80400000; /* get config bits */
/*
* Restore GPIO settings
*/
- out32(GPIO0_OSRH, osrh_reg); /* output select */
- out32(GPIO0_ISR1H, isr1h_reg); /* input select */
- out32(GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
+ out_be32((void *)GPIO0_OSRH, osrh_reg); /* output select */
+ out_be32((void *)GPIO0_ISR1H, isr1h_reg); /* input select */
+ out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */
* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
- mtebc (epcr, 0xa8400000); /* ebc always driven */
+ mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
return 0;
}
{
int i;
- volatile unsigned short *fpga_ctrl =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- volatile unsigned short *fpga_status =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
-
if (gd->board_type >= 2) {
- if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) {
- if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) {
- *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN;
+ if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
+ if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
for (i=0; i<300; i++)
udelay(1000);
- *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
for (i=0; i<20; i++)
udelay(1000);
}
} else {
- *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
- *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
}
}
int misc_init_r (void)
{
- volatile unsigned short *fpga_ctrl =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- volatile unsigned short *lcd_contrast =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
- volatile unsigned short *lcd_backlight =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
unsigned char *dst;
ulong len = sizeof(fpgadata);
int status;
/*
* Reset FPGA via FPGA_INIT pin
*/
- out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~FPGA_INIT); /* reset low */
+ /* setup FPGA_INIT as output */
+ out_be32((void *)GPIO0_TCR,
+ in_be32((void *)GPIO0_TCR) | FPGA_INIT);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~FPGA_INIT); /* reset low */
udelay(1000); /* wait 1ms */
- out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_INIT); /* reset high */
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | FPGA_INIT); /* reset high */
udelay(1000); /* wait 1ms */
/*
* Write Board revision into FPGA
*/
- *fpga_ctrl |= gd->board_type & 0x0003;
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
/*
* Setup and enable EEPROM write protection
*/
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
/*
* Reset touch-screen controller
*/
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
udelay(1000);
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
/*
* Enable power on PS/2 interface (with reset)
*/
- *fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR);
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
for (i=0;i<500;i++)
udelay(1000);
- *fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR);
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
/*
* Get contrast value from environment variable
if (str) {
contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) {
- printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
+ printf("ERROR: contrast0 value too high (0x%lx)!\n",
+ contrast0);
contrast0 = 0xffffffff;
}
}
/*
* Switch backlight on
*/
- *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL;
- *lcd_backlight = 0x0000;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
+ out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
/*
* Switch backlight on
*/
- *fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL;
- *lcd_backlight = 0x0000;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
+ out_be16(FPGA_BL, 0x0000);
lcd_setup(1, 0);
lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
- *lcd_contrast = 0x0082;
+ out_be16(FPGA_CTR, 0x0082);
} else {
- *lcd_contrast = contrast0;
+ out_be16(FPGA_CTR, contrast0);
}
- *lcd_backlight = 0xffff;
+ out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
- *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_VGA0_BL |
+ FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson)
*/
- *fpga_ctrl |= LCD_CLK_06250;
+ out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
udelay(100); /* wait for 100 us */
lcd_setup(0, 1);
* Set default display contrast voltage
*/
if (contrast0 == 0xffffffff) {
- *lcd_contrast = 0x0060;
+ out_be16(FPGA_CTR, 0x0060);
} else {
- *lcd_contrast = contrast0;
+ out_be16(FPGA_CTR, contrast0);
}
- *lcd_backlight = 0xffff;
+ out_be16(FPGA_BL, 0xffff);
/*
* Switch backlight on
*/
- *fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_VGA0_BL |
+ FPGA_CTRL_VGA0_BL_MODE);
/*
* Set lcd clock (small epson), enable 1-wire interface
*/
- *fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ LCD_CLK_08330 |
+ FPGA_CTRL_OW_ENABLE);
lcd_setup(0, 1);
lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP);
- *lcd_backlight = 0x002d; /* max. allowed brightness */
+ out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP);
- *lcd_backlight = 0x0000;
+ out_be16(FPGA_BL, 0x0000);
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
int checkboard (void)
{
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
puts(str);
}
- if (getenv_r("bd_type", str, sizeof(str)) != -1) {
+ if (getenv_f("bd_type", str, sizeof(str)) != -1) {
printf(" (%s", str);
} else {
puts(" (Missing bd_type!");
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
- volatile unsigned short *fpga_mode =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
- volatile unsigned short *fpga_status =
- (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
-
- if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) ||
+ if (((gd->board_type >= 2) &&
+ (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
(gd->board_type < 2)) {
/*
* Assert or deassert CompactFlash Reset Pin
*/
if (on) { /* assert RESET */
cf_enable();
- *fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) &
+ ~FPGA_CTRL_CF_RESET);
} else { /* release RESET */
- *fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
+ out_be16(FPGA_CTRL,
+ in_be16(FPGA_CTRL) |
+ FPGA_CTRL_CF_RESET);
}
}
}
switch (state) {
case 1:
/* Enable write access, clear bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
state = 0;
break;
case 0:
/* Disable write access, set bit GPIO_SINT2. */
- out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+ out_be32((void *)GPIO0_OR,
+ in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
state = 0;
break;
default:
/* Read current status back. */
- state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
+ state = (0 == (in_be32((void *)GPIO0_OR) &
+ CONFIG_SYS_EEPROM_WP));
break;
}
}
return state;
}
-int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int query = argc == 1;
int state = 0;
}
U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
- "Enable / disable / query EEPROM write access",
- NULL);
+ "Enable / disable / query EEPROM write access",
+ ""
+);
#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
{
char str[64];
char str2[64];
- int i = getenv_r("serial#", str2, sizeof(str));
+ int i = getenv_f("serial#", str2, sizeof(str));
if (line_number == 1) {
sprintf(str, " Board: ");
strcat(str, str2);
}
- if (getenv_r("bd_type", str2, sizeof(str2)) != -1) {
+ if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
strcat(str, " (");
strcat(str, str2);
} else {
projects / karo-tx-uboot.git / blobdiff