ppc4xx: Big header cleanup, mostly PPC440 related

[karo-tx-uboot.git] / board / esd / pci405 / pci405.c

diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index 0602abf9c4806ea02cc23d8e1a1e94945eb36bad..4018a7d29fd5ddae0a3ee57c6693084fd94425d5 100644 (file)
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -34,8 +34,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* Prototypes */
-int gunzip(void *, int, unsigned char *, unsigned long *);
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 unsigned long fpga_done_state(void);
 unsigned long fpga_init_state(void);
 
@@ -67,7 +66,7 @@ const unsigned char fpgadata[] =
 
 int board_revision(void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
        unsigned long value;
 
        /*
@@ -77,8 +76,8 @@ int board_revision(void)
        /*
         * Setup GPIO pins (CS2/GPIO11 and CS3/GPIO12 as GPIO)
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x03000000);
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x03000000);
        out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00100200);
        out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00100200);
        udelay(1000);                   /* wait some time before reading input */
@@ -87,7 +86,7 @@ int board_revision(void)
        /*
         * Restore GPIO settings
         */
-       mtdcr(cntrl0, cntrl0Reg);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg);
 
        switch (value) {
        case 0x00100200:
@@ -133,7 +132,7 @@ unsigned long fpga_init_state(void)
 
 int board_early_init_f (void)
 {
-       unsigned long cntrl0Reg;
+       unsigned long CPC0_CR0Reg;
 
        /*
         * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
@@ -155,29 +154,29 @@ int board_early_init_f (void)
         * IRQ 30 (EXT IRQ 5) FPGA Timestamp; active low; level sensitive
         * IRQ 31 (EXT IRQ 6) PCI Reset; active low; level sensitive
         */
-       mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
-       mtdcr(uicer, 0x00000000);        /* disable all ints */
-       mtdcr(uiccr, 0x00000000);        /* set all to be non-critical*/
-       mtdcr(uicpr, 0xFFFFFF80);        /* set int polarities */
-       mtdcr(uictr, 0x10000000);        /* set int trigger levels */
-       mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
-       mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+       mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
+       mtdcr(UIC0ER, 0x00000000);        /* disable all ints */
+       mtdcr(UIC0CR, 0x00000000);        /* set all to be non-critical*/
+       mtdcr(UIC0PR, 0xFFFFFF80);        /* set int polarities */
+       mtdcr(UIC0TR, 0x10000000);        /* set int trigger levels */
+       mtdcr(UIC0VCR, 0x00000001);       /* set vect base=0,INT0 highest priority*/
+       mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
        /*
         * Setup GPIO pins (IRQ4/GPIO21 as GPIO)
         */
-       cntrl0Reg = mfdcr(cntrl0);
-       mtdcr(cntrl0, cntrl0Reg | 0x00008000);
+       CPC0_CR0Reg = mfdcr(CPC0_CR0);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00008000);
 
        /*
         * Setup GPIO pins (CS6+CS7 as GPIO)
         */
-       mtdcr(cntrl0, cntrl0Reg | 0x00300000);
+       mtdcr(CPC0_CR0, CPC0_CR0Reg | 0x00300000);
 
        /*
         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 25 us
         */
-       mtebc (epcr, 0xa8400000); /* ebc always driven */
+       mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
 
        return 0;
 }
@@ -271,7 +270,7 @@ int misc_init_r (void)
                                pci_write_config_dword(PCIDEVID_405GP, i, *ptr++);
                        }
                }
-               mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
+               mtdcr(UIC0SR, 0xFFFFFFFF);        /* clear all ints */
 
                *magic = 0;      /* clear pci reconfig magic again */
        }
@@ -282,11 +281,10 @@ int misc_init_r (void)
 #define PCI0_BRDGOPT1 0x4a
        pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20);
 
-#define plb0_acr      0x87
        /*
         * Enable fairness and high bus utilization
         */
-       mtdcr(plb0_acr, 0x98000000);
+       mtdcr(PLB0_ACR, 0x98000000);
 
        free(dst);
        return (0);
@@ -299,7 +297,7 @@ int misc_init_r (void)
 int checkboard (void)
 {
        char str[64];
-       int i = getenv_r ("serial#", str, sizeof(str));
+       int i = getenv_f("serial#", str, sizeof(str));
 
        puts ("Board: ");
 
@@ -313,14 +311,14 @@ int checkboard (void)
        printf(" (Rev 1.%ld", gd->board_type);
 
        if (gd->board_type >= 2) {
-               unsigned long cntrl0Reg;
+               unsigned long CPC0_CR0Reg;
                unsigned long value;
 
                /*
                 * Setup GPIO pins (Trace/GPIO1 to GPIO)
                 */
-               cntrl0Reg = mfdcr(cntrl0);
-               mtdcr(cntrl0, cntrl0Reg & ~0x08000000);
+               CPC0_CR0Reg = mfdcr(CPC0_CR0);
+               mtdcr(CPC0_CR0, CPC0_CR0Reg & ~0x08000000);
                out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x40000000);
                out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x40000000);
                udelay(1000);                   /* wait some time before reading input */
@@ -338,17 +336,17 @@ int checkboard (void)
 }
 
 /* ------------------------------------------------------------------------- */
+#define UART1_MCR 0xef600404
 int wpeeprom(int wp)
 {
        int wp_state = wp;
-       volatile unsigned char *uart1_mcr = (volatile unsigned char *)0xef600404;
 
        if (wp == 1) {
-               *uart1_mcr &= ~0x02;
+               out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) & ~0x02);
        } else if (wp == 0) {
-               *uart1_mcr |= 0x02;
+               out_8((void *)UART1_MCR, in_8((void *)UART1_MCR) | 0x02);
        } else {
-               if (*uart1_mcr & 0x02) {
+               if (in_8((void *)UART1_MCR) & 0x02) {
                        wp_state = 0;
                } else {
                        wp_state = 1;
@@ -357,7 +355,7 @@ int wpeeprom(int wp)
        return wp_state;
 }
 
-int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_wpeeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
        int wp = -1;
        if (argc >= 2) {
@@ -381,5 +379,5 @@ U_BOOT_CMD(
        "wpeeprom 1\n"
        "    - enable I2C EEPROM write protection\n"
        "wpeeprom 0\n"
-       "    - disable I2C EEPROM write protection\n"
-       );
+       "    - disable I2C EEPROM write protection"
+);