#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#define EMI1_MASK 0xc0000000
#define EMI2_MASK 0x30000000
+#define PHY_BASE_ADDR 0x00
+#define PHY_BASE_ADDR_SLOT5 0x10
+
static int mdio_mux[NUM_FM_PORTS];
static char *mdio_names[16] = {
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
+ struct mii_dev *bus;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
break;
}
}
+ bus = mii_dev_for_muxval(EMI1_SLOT5);
+ set_sgmii_phy(bus, FM1_DTSEC1,
+ CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR_SLOT5);
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1, lane, slot;
}
}
+ bus = mii_dev_for_muxval(EMI1_SLOT3);
+ set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+ bus = mii_dev_for_muxval(EMI1_SLOT4);
+ set_sgmii_phy(bus, FM2_DTSEC1, CONFIG_SYS_NUM_FM2_DTSEC, PHY_BASE_ADDR);
+
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
int idx = i - FM2_10GEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {