Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

[karo-tx-uboot.git] / board / freescale / ls1021aqds / ddr.c

diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c
index 679c654fb57227f579e1c656afa515fd96099384..a539ff97913ded4a98b3e95ca0ea9cafc8f05175 100644 (file)
--- a/board/freescale/ls1021aqds/ddr.c
+++ b/board/freescale/ls1021aqds/ddr.c
@@ -79,7 +79,6 @@ found:
         */
        popts->wrlvl_override = 1;
        popts->wrlvl_sample = 0xf;
-       popts->cswl_override = DDR_CSWL_CS0;
 
        /*
         * Rtt and Rtt_WR override
@@ -89,9 +88,17 @@ found:
        /* Enable ZQ calibration */
        popts->zq_en = 1;
 
+#ifdef CONFIG_SYS_FSL_DDR4
+       popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+       popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
+                         DDR_CDR2_VREF_OVRD(70);       /* Vref = 70% */
+#else
+       popts->cswl_override = DDR_CSWL_CS0;
+
        /* DHC_EN =1, ODT = 75 Ohm */
        popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+#endif
 }
 
 #ifdef CONFIG_SYS_DDR_RAW_TIMING
@@ -146,9 +153,12 @@ phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
 
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
        puts("Initializing DDR....using SPD\n");
        dram_size = fsl_ddr_sdram();
-
+#else
+       dram_size =  fsl_ddr_sdram_size();
+#endif
        return dram_size;
 }