/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_pci.h>
#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_mdio.h>
#include <tsec.h>
#include <netdev.h>
-#include "../common/pixis.h"
#include "../common/sgmii_riser.h"
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-extern void ddr_enable_ecc(unsigned int dram_size);
-#endif
-
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+ u8 vboot;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %lx\n",(ulong)&gur->porpllsr);
}
- printf ("Board: MPC8544DS, System ID: 0x%02x, "
- "System Version: 0x%02x, FPGA Version: 0x%02x\n",
- in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
- in8(PIXIS_BASE + PIXIS_PVER));
+ printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
+ "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
+ in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
+ in_8(pixis_base + PIXIS_PVER));
+
+ vboot = in_8(pixis_base + PIXIS_VBOOT);
+ if (vboot & PIXIS_VBOOT_FMAP)
+ printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
+ else
+ puts ("Promjet\n");
lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
return 0;
}
-phys_size_t
-initdram(int board_type)
-{
- long dram_size = 0;
-
- puts("Initializing\n");
-
- dram_size = fsl_ddr_sdram();
-
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
-
- dram_size *= 0x100000;
-
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
- /*
- * Initialize and enable DDR ECC.
- */
- ddr_enable_ecc(dram_size);
-#endif
- puts(" DDR: ");
- return dram_size;
-}
-
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
#endif
-#ifdef CONFIG_PCIE1
-static struct pci_controller pcie1_hose;
-#endif
-
-#ifdef CONFIG_PCIE2
-static struct pci_controller pcie2_hose;
-#endif
-
#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif
-int first_free_busno=0;
-
-void
-pci_init_board(void)
+void pci_init_board(void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- uint devdisr = gur->devdisr;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-
- debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
- devdisr, io_sel, host_agent);
-
- if (io_sel & 1) {
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
- printf (" eTSEC1 is in sgmii mode.\n");
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
- printf (" eTSEC3 is in sgmii mode.\n");
- }
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ struct fsl_pci_info pci_info;
+ u32 devdisr, pordevsr, io_sel;
+ u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
+ int first_free_busno = 0;
-#ifdef CONFIG_PCIE3
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pcie3_hose;
- int pcie_ep = (host_agent == 1);
- int pcie_configured = io_sel >= 1;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE3 connected to ULI as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
+ int pcie_ep, pcie_configured;
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCIE3_MEM_BASE,
- CFG_PCIE3_MEM_PHYS,
- CFG_PCIE3_MEM_SIZE,
- PCI_REGION_MEM);
+ devdisr = in_be32(&gur->devdisr);
+ pordevsr = in_be32(&gur->pordevsr);
+ porpllsr = in_be32(&gur->porpllsr);
+ io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCIE3_IO_BASE,
- CFG_PCIE3_IO_PHYS,
- CFG_PCIE3_IO_SIZE,
- PCI_REGION_IO);
+ debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+ puts("\n");
+
+#ifdef CONFIG_PCIE3
+ pcie_configured = is_serdes_configured(PCIE3);
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
+ /* contains both PCIE3 MEM & IO space */
+ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
+ LAW_TRGT_IF_PCIE_3);
+ SET_STD_PCIE_INFO(pci_info, 3);
+ pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
- hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
/* outbound memory */
- pci_set_region(hose->regions + 3,
- CFG_PCIE3_MEM_BASE2,
- CFG_PCIE3_MEM_PHYS2,
- CFG_PCIE3_MEM_SIZE2,
+ pci_set_region(&pcie3_hose.regions[0],
+ CONFIG_SYS_PCIE3_MEM_BUS2,
+ CONFIG_SYS_PCIE3_MEM_PHYS2,
+ CONFIG_SYS_PCIE3_MEM_SIZE2,
PCI_REGION_MEM);
- hose->region_count++;
-#endif
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
- fsl_pci_init(hose);
+ pcie3_hose.region_count = 1;
- first_free_busno=hose->last_busno+1;
- printf (" PCIE3 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
+ pcie_ep ? "Endpoint" : "Root Complex",
+ pci_info.regs);
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pcie3_hose, first_free_busno);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
*/
- in_be32((u32 *)CFG_PCIE3_MEM_BASE);
+ in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
} else {
- printf (" PCIE3: disabled\n");
+ printf("PCIE3: disabled\n");
}
-
- }
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE1
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pcie1_hose;
- int pcie_ep = (host_agent == 5);
- int pcie_configured = io_sel & 6;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCIE1_MEM_BASE,
- CFG_PCIE1_MEM_PHYS,
- CFG_PCIE1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCIE1_IO_BASE,
- CFG_PCIE1_IO_PHYS,
- CFG_PCIE1_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
- /* outbound memory */
- pci_set_region(hose->regions + 3,
- CFG_PCIE1_MEM_BASE2,
- CFG_PCIE1_MEM_PHYS2,
- CFG_PCIE1_MEM_SIZE2,
- PCI_REGION_MEM);
- hose->region_count++;
-#endif
- hose->first_busno=first_free_busno;
-
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
-
- first_free_busno=hose->last_busno+1;
- printf(" PCIE1 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
- } else {
- printf (" PCIE1: disabled\n");
- }
-
- }
+ SET_STD_PCIE_INFO(pci_info, 1);
+ first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+ setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
#endif
#ifdef CONFIG_PCIE2
- {
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pcie2_hose;
- int pcie_ep = (host_agent == 3);
- int pcie_configured = io_sel & 4;
-
- if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
- printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
- pcie_ep ? "End Point" : "Root Complex",
- (uint)pci);
- if (pci->pme_msg_det) {
- pci->pme_msg_det = 0xffffffff;
- debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
- }
- printf ("\n");
-
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCIE2_MEM_BASE,
- CFG_PCIE2_MEM_PHYS,
- CFG_PCIE2_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCIE2_IO_BASE,
- CFG_PCIE2_IO_PHYS,
- CFG_PCIE2_IO_SIZE,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-#ifdef CFG_PCIE2_MEM_BASE2
- /* outbound memory */
- pci_set_region(hose->regions + 3,
- CFG_PCIE2_MEM_BASE2,
- CFG_PCIE2_MEM_PHYS2,
- CFG_PCIE2_MEM_SIZE2,
- PCI_REGION_MEM);
- hose->region_count++;
-#endif
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- first_free_busno=hose->last_busno+1;
- printf (" PCIE2 on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
-
- } else {
- printf (" PCIE2: disabled\n");
- }
-
- }
+ SET_STD_PCIE_INFO(pci_info, 2);
+ first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+ setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
#endif
-
#ifdef CONFIG_PCI1
-{
- volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
- extern void fsl_pci_init(struct pci_controller *hose);
- struct pci_controller *hose = &pci1_hose;
-
- uint pci_agent = (host_agent == 6);
- uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
- uint pci_32 = 1;
- uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
- uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
-
+ pci_speed = 66666000;
+ pci_32 = 1;
+ pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
+ pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
- printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ SET_STD_PCI_INFO(pci_info, 1);
+ set_next_law(pci_info.mem_phys,
+ law_size_bits(pci_info.mem_size), pci_info.law);
+ set_next_law(pci_info.io_phys,
+ law_size_bits(pci_info.io_size), pci_info.law);
+
+ pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
+ printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
(pci_32) ? 32 : 64,
(pci_speed == 33333000) ? "33" :
(pci_speed == 66666000) ? "66" : "unknown",
pci_clk_sel ? "sync" : "async",
pci_agent ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter",
- (uint)pci
- );
+ pci_info.regs);
- /* inbound */
- pci_set_region(hose->regions + 0,
- CFG_PCI_MEMORY_BUS,
- CFG_PCI_MEMORY_PHYS,
- CFG_PCI_MEMORY_SIZE,
- PCI_REGION_MEM | PCI_REGION_MEMORY);
-
- /* outbound memory */
- pci_set_region(hose->regions + 1,
- CFG_PCI1_MEM_BASE,
- CFG_PCI1_MEM_PHYS,
- CFG_PCI1_MEM_SIZE,
- PCI_REGION_MEM);
-
- /* outbound io */
- pci_set_region(hose->regions + 2,
- CFG_PCI1_IO_BASE,
- CFG_PCI1_IO_PHYS,
- CFG_PCI1_IO_SIZE,
- PCI_REGION_IO);
- hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
- /* outbound memory */
- pci_set_region(hose->regions + 3,
- CFG_PCIE3_MEM_BASE2,
- CFG_PCIE3_MEM_PHYS2,
- CFG_PCIE3_MEM_SIZE2,
- PCI_REGION_MEM);
- hose->region_count++;
-#endif
- hose->first_busno=first_free_busno;
- pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
-
- fsl_pci_init(hose);
- first_free_busno=hose->last_busno+1;
- printf ("PCI on bus %02x - %02x\n",
- hose->first_busno,hose->last_busno);
+ first_free_busno = fsl_pci_init_port(&pci_info,
+ &pci1_hose, first_free_busno);
} else {
- printf (" PCI: disabled\n");
+ printf("PCI: disabled\n");
}
-}
+
+ puts("\n");
#else
- gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
#endif
}
-
int last_stage_init(void)
{
return 0;
{
u8 i, go_bit, rd_clks;
ulong val = 0;
+ u8 *pixis_base = (u8 *)PIXIS_BASE;
- go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
+ go_bit = in_8(pixis_base + PIXIS_VCTL);
go_bit &= 0x01;
- rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
+ rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
rd_clks &= 0x1C;
/*
if (go_bit) {
if (rd_clks == 0x1c)
- i = in8(PIXIS_BASE + PIXIS_AUX);
+ i = in_8(pixis_base + PIXIS_AUX);
else
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
} else {
- i = in8(PIXIS_BASE + PIXIS_SPD);
+ i = in_8(pixis_base + PIXIS_SPD);
}
i &= 0x07;
return val;
}
+
+#define MIIM_CIS8204_SLED_CON 0x1b
+#define MIIM_CIS8204_SLEDCON_INIT 0x1115
+/*
+ * Hack to write all 4 PHYs with the LED values
+ */
+int board_phy_config(struct phy_device *phydev)
+{
+ static int do_once;
+ uint phyid;
+ struct mii_dev *bus = phydev->bus;
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ if (do_once)
+ return 0;
+
+ for (phyid = 0; phyid < 4; phyid++)
+ bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
+ MIIM_CIS8204_SLEDCON_INIT);
+
+ do_once = 1;
+
+ return 0;
+}
+
+
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_TSEC_ENET
+ struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[2];
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ if (is_serdes_configured(SGMII_TSEC1)) {
+ puts("eTSEC1 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
+ }
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
- if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ if (is_serdes_configured(SGMII_TSEC3)) {
+ puts("eTSEC3 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
+ }
num++;
#endif
return 0;
}
- if (io_sel & 1)
+ if (is_serdes_configured(SGMII_TSEC1) ||
+ is_serdes_configured(SGMII_TSEC3)) {
fsl_sgmii_riser_init(tsec_info, num);
+ }
+ mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+ mdio_info.name = DEFAULT_MII_NAME;
+ fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
}
#if defined(CONFIG_OF_BOARD_SETUP)
-
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
{
- int node, tmp[2];
- const char *path;
-
ft_cpu_setup(blob, bd);
- node = fdt_path_offset(blob, "/aliases");
- tmp[0] = 0;
- if (node >= 0) {
-#ifdef CONFIG_PCI1
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
-#ifdef CONFIG_PCIE2
- path = fdt_getprop(blob, node, "pci1", NULL);
- if (path) {
- tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
-#ifdef CONFIG_PCIE1
- path = fdt_getprop(blob, node, "pci2", NULL);
- if (path) {
- tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
-#ifdef CONFIG_PCIE3
- path = fdt_getprop(blob, node, "pci3", NULL);
- if (path) {
- tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
+ FT_FSL_PCI_SETUP;
+
+#ifdef CONFIG_FSL_SGMII_RISER
+ fsl_sgmii_riser_fdt_fixup(blob);
#endif
- }
}
#endif