#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
+#include <pmic.h>
#include <fsl_pmic.h>
-#include <mxc_gpio.h>
+#include <asm/gpio.h>
#include <mc13892.h>
DECLARE_GLOBAL_DATA_PTR;
-u32 get_board_rev(void)
-{
- return get_cpu_rev();
-}
-
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
void power_init(void)
{
unsigned int val;
+ struct pmic *p;
+
+ pmic_init();
+ p = get_pmic();
/* Set VDDA to 1.25V */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_25;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
/*
* Need increase VCC and VDDA to 1.3V
*/
if (is_soc_rev(CHIP_REV_2_0) == 0) {
/* Set VCC to 1.3V for TO2 */
- val = pmic_reg_read(REG_SW_1);
+ pmic_reg_read(p, REG_SW_1, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
- pmic_reg_write(REG_SW_1, val);
+ pmic_reg_write(p, REG_SW_1, val);
/* Set VDDA to 1.3V for TO2 */
- val = pmic_reg_read(REG_SW_2);
+ pmic_reg_read(p, REG_SW_2, &val);
val &= ~SWX_OUT_MASK;
val |= SWX_OUT_1_30;
- pmic_reg_write(REG_SW_2, val);
+ pmic_reg_write(p, REG_SW_2, val);
}
}
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
+ mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
+
if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
- *cd = mxc_gpio_get(77); /*GPIO3_13*/
+ *cd = gpio_get_value(77); /*GPIO3_13*/
else
- *cd = mxc_gpio_get(75); /*GPIO3_11*/
+ *cd = gpio_get_value(75); /*GPIO3_11*/
return 0;
}
int board_init(void)
{
- gd->bd->bi_arch_number = MACH_TYPE_MX53_EVK;
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;