Merge branch 'master' of git://git.denx.de/u-boot

[karo-tx-uboot.git] / board / freescale / p1_p2_rdb / tlb.c

diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index cf9bffed5f7505dbfc925340d88b44671491a74f..1847935a73761b646437c9299e321b818086ef6a 100644 (file)
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2011 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,26 +25,27 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
        /* TLB 0 - for temp stack in cache */
-       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+       SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
        SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
                        MAS3_SX|MAS3_SW|MAS3_SR, 0,
                        0, 0, BOOKE_PAGESZ_4K, 0),
 
        /* TLB 1 */
        /* *I*** - Covers boot page */
        SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 0, BOOKE_PAGESZ_4K, 1),
 
        /* *I*G* - CCSRBAR */
@@ -58,16 +59,18 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                        0, 2, BOOKE_PAGESZ_16M, 1),
 
+#if defined(CONFIG_PCI)
        /* *I*G* - PCI */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 3, BOOKE_PAGESZ_1G, 1),
 
        /* *I*G* - PCI I/O */
-       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+       SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 4, BOOKE_PAGESZ_256K, 1),
 
+#endif /* #if defined(CONFIG_PCI) */
        /* *I*G - NAND */
        SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -78,6 +81,11 @@ struct fsl_e_tlb_entry tlb_table[] = {
                        MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
                        0, 6, BOOKE_PAGESZ_1M, 1),
 
+#if defined(CONFIG_SYS_RAMBOOT)
+       SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, 7, BOOKE_PAGESZ_1G, 1)
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);