Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

[karo-tx-uboot.git] / board / freescale / t4qds / ddr.c

diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index 692616aed4d88f0f58a65f6a14ceef9c178bd203..058d62511f5979fef8c9fc72502af540b79aed33 100644 (file)
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -19,6 +19,7 @@ DECLARE_GLOBAL_DATA_PTR;
 struct board_specific_parameters {
        u32 n_ranks;
        u32 datarate_mhz_high;
+       u32 rank_gb;
        u32 clk_adjust;
        u32 wrlvl_start;
        u32 wrlvl_ctl_2;
@@ -36,16 +37,19 @@ struct board_specific_parameters {
 static const struct board_specific_parameters udimm0[] = {
        /*
         * memory controller 0
-        *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
-       {2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-       {1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+       {2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+       {2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+       {2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+       {2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+       {2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+       {2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+       {1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+       {1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+       {1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+       {1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
        {}
 };
 
@@ -61,19 +65,19 @@ static const struct board_specific_parameters *udimms[] = {
 static const struct board_specific_parameters rdimm0[] = {
        /*
         * memory controller 0
-        *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
-        * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
         */
-       {4,  1350,    5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
-       {4,  1666,    5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
-       {4,  2140,    5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
-       {2,  1350,    5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
-       {2,  1666,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {2,  2140,    5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
-       {1,  1350,    5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-       {1,  1700,    5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-       {1,  1900,    4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-       {1,  2140,    4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+       {4,  1350, 0, 5,     9, 0x08070605, 0x07080805,   0xff,    2,  0},
+       {4,  1666, 0, 5,     8, 0x08070605, 0x07080805,   0xff,    2,  0},
+       {4,  2140, 0, 5,     8, 0x08070605, 0x07081805,   0xff,    2,  0},
+       {2,  1350, 0, 5,     7, 0x0809090b, 0x0c0c0d09,   0xff,    2,  0},
+       {2,  1666, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+       {2,  2140, 0, 5,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+       {1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+       {1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+       {1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+       {1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
        {}
 };
 
@@ -113,7 +117,8 @@ void fsl_ddr_board_options(memctl_options_t *popts,
         */
        ddr_freq = get_ddr_freq(0) / 1000000;
        while (pbsp->datarate_mhz_high) {
-               if (pbsp->n_ranks == pdimm->n_ranks) {
+               if (pbsp->n_ranks == pdimm->n_ranks &&
+                   (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
                        if (ddr_freq <= pbsp->datarate_mhz_high) {
                                popts->cpo_override = pbsp->cpo;
                                popts->write_data_delay =
@@ -146,6 +151,13 @@ void fsl_ddr_board_options(memctl_options_t *popts,
                panic("DIMM is not supported by this board");
        }
 found:
+       debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+               "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+               "wrlvl_ctrl_3 0x%x\n",
+               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+               pbsp->wrlvl_ctl_3);
+
        /*
         * Factors to consider for half-strength driver enable:
         *      - number of DIMMs installed