Merge 'u-boot-microblaze/zynq' into (u-boot-arm/master'

[karo-tx-uboot.git] / board / freescale / t4qds / t4240qds.c

diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c
index 7ee0f547866913edb03d56df021d308376a69525..0c1a4fbd9ff7b4f6a44656f740290a8e15f23f15 100644 (file)
--- a/board/freescale/t4qds/t4240qds.c
+++ b/board/freescale/t4qds/t4240qds.c
@@ -26,16 +26,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
+static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
                                {8, 8}, {9, 9}, {14, 14}, {15, 15} };
 
-static const int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
+static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
                                {10, 10}, {11, 11}, {12, 12}, {13, 13} };
 
-static const int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
+static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
                                {10, 11}, {11, 10}, {12, 2}, {13, 3} };
 
-static const int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
+static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
                                {8, 9}, {9, 8}, {14, 1}, {15, 0} };
 
 int checkboard(void)
@@ -353,25 +353,60 @@ int config_frontside_crossbar_vsc3316(void)
        srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
                        FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
        srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
-       if (srds_prtcl_s1) {
+       switch (srds_prtcl_s1) {
+       case 38:
+               /* swap first lane and third lane on slot1 */
+               vsc3316_fsm1_tx[0][1] = 14;
+               vsc3316_fsm1_tx[6][1] = 0;
+               vsc3316_fsm1_rx[1][1] = 2;
+               vsc3316_fsm1_rx[6][1] = 13;
+       case 40:
+       case 46:
+       case 48:
+               /* swap first lane and third lane on slot2 */
+               vsc3316_fsm1_tx[2][1] = 8;
+               vsc3316_fsm1_tx[4][1] = 6;
+               vsc3316_fsm1_rx[2][1] = 10;
+               vsc3316_fsm1_rx[5][1] = 5;
+       default:
                ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
                if (ret)
                        return ret;
                ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
                if (ret)
                        return ret;
+               break;
        }
 
        srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
                                FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
        srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
-       if (srds_prtcl_s2) {
+       switch (srds_prtcl_s2) {
+       case 38:
+               /* swap first lane and third lane on slot3 */
+               vsc3316_fsm2_tx[2][1] = 11;
+               vsc3316_fsm2_tx[5][1] = 4;
+               vsc3316_fsm2_rx[2][1] = 9;
+               vsc3316_fsm2_rx[4][1] = 7;
+       case 40:
+       case 46:
+       case 48:
+       case 50:
+       case 52:
+       case 54:
+               /* swap first lane and third lane on slot4 */
+               vsc3316_fsm2_tx[6][1] = 3;
+               vsc3316_fsm2_tx[1][1] = 12;
+               vsc3316_fsm2_rx[0][1] = 1;
+               vsc3316_fsm2_rx[6][1] = 15;
+       default:
                ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
                if (ret)
                        return ret;
                ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
                if (ret)
                        return ret;
+               break;
        }
 
        return 0;