* (C) Copyright 2004
* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
int board_early_init_f (void)
{
#if 0 /* test-only */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr (uicer, 0x00000000); /* disable all ints */
- mtdcr (uiccr, 0x00000010);
- mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */
- mtdcr (uictr, 0x00000010); /* set int trigger levels */
- mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr (UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr (UIC0CR, 0x00000010);
+ mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
+ mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
+ mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
#else
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
- mtdcr(uicpr, 0xFFFFFFF0); /* set int polarities */
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(UIC0ER, 0x00000000); /* disable all ints */
+ mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
+ mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
+ mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
+ mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
#endif
#if 1 /* test-only */
/*
* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
*/
- mtebc (epcr, 0xa8400000); /* ebc always driven */
+ mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
#endif
return 0;
int checkboard (void)
{
char str[64];
- int i = getenv_r ("serial#", str, sizeof(str));
+ int i = getenv_f("serial#", str, sizeof(str));
puts ("Board: ");
long int init_sdram_static_settings(void)
{
-#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
/* disable memcontroller so updates work */
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL );
- mtsdram0( mem_rtr , MEM_RTR_INIT_VAL );
- mtsdram0( mem_pmit , MEM_PMIT_INIT_VAL );
- mtsdram0( mem_mb0cf , MEM_MB0CF_INIT_VAL );
- mtsdram0( mem_mb1cf , MEM_MB1CF_INIT_VAL );
- mtsdram0( mem_sdtr1 , MEM_SDTR1_INIT_VAL );
+ mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
+ mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
+ mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
+ mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
+ mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
+ mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
/* SDRAM have a power on delay, 500 micro should do */
udelay(500);
- mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
+ mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
}
return ret;
}
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
-
-void nand_init(void)
-{
- nand_probe(CONFIG_SYS_NAND_BASE);
- if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
- print_size(nand_dev_desc[0].totlen, "\n");
- }
-}
-#endif
-
-
#if 0 /* test-only !!! */
-int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong ap, cr;
printf("\nEBC registers for PPC405GP:\n");
- mfebc(pb0ap, ap); mfebc(pb0cr, cr);
+ mfebc(PB0AP, ap); mfebc(PB0CR, cr);
printf("0: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(pb1ap, ap); mfebc(pb1cr, cr);
+ mfebc(PB1AP, ap); mfebc(PB1CR, cr);
printf("1: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(pb2ap, ap); mfebc(pb2cr, cr);
+ mfebc(PB2AP, ap); mfebc(PB2CR, cr);
printf("2: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(pb3ap, ap); mfebc(pb3cr, cr);
+ mfebc(PB3AP, ap); mfebc(PB3CR, cr);
printf("3: AP=%08lx CP=%08lx\n", ap, cr);
- mfebc(pb4ap, ap); mfebc(pb4cr, cr);
+ mfebc(PB4AP, ap); mfebc(PB4CR, cr);
printf("4: AP=%08lx CP=%08lx\n", ap, cr);
printf("\n");
U_BOOT_CMD(
dumpebc, 1, 1, do_dumpebc,
"Dump all EBC registers",
- NULL
+ ""
);
-int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int i;
U_BOOT_CMD(
dumpdcr, 1, 1, do_dumpdcr,
"Dump all DCR registers",
- NULL
+ ""
);
-int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
printf("\n%04x %08x ", 947, mfspr(947));
U_BOOT_CMD(
dumpspr, 1, 1, do_dumpspr,
"Dump all SPR registers",
- NULL
+ ""
);
#endif