gic: fixed compilation error in GICv2 wait for interrupt macro

[karo-tx-uboot.git] / board / icu862 / icu862.c

diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c
index 8da9d1c9a49f70882781c0b198c7e9c9a114573a..4c0e919739e28d65efd1fca5d60f5a1dd4f721eb 100644 (file)
--- a/board/icu862/icu862.c
+++ b/board/icu862/icu862.c
@@ -2,23 +2,7 @@
  * (C) Copyright 2001
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -94,9 +78,9 @@ static long int dram_size (long int, long int *, long int);
 
 /* ------------------------------------------------------------------------- */
 
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
        long int size8, size9;
        long int size_b0 = 0;
@@ -111,7 +95,7 @@ long int initdram (int board_type)
         * with two SDRAM banks or four cycles every 31.2 us with one
         * bank. It will be adjusted after memory sizing.
         */
-       memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+       memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
        memctl->memc_mar = 0x00000088;
 
@@ -120,10 +104,10 @@ long int initdram (int board_type)
         * preliminary address - these have to be modified after the
         * SDRAM size has been determined.
         */
-       memctl->memc_or1 = CFG_OR1_PRELIM;
-       memctl->memc_br1 = CFG_BR1_PRELIM;
+       memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+       memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-       memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));     /* no refresh yet */
+       memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));      /* no refresh yet */
 
        udelay (200);
 
@@ -143,7 +127,7 @@ long int initdram (int board_type)
         *
         * try 8 column mode
         */
-       size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
+       size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
                                           SDRAM_MAX_SIZE);
 
        udelay (1000);
@@ -151,7 +135,7 @@ long int initdram (int board_type)
        /*
         * try 9 column mode
         */
-       size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
+       size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
                                           SDRAM_MAX_SIZE);
 
        if (size8 < size9) {            /* leave configuration at 9 columns */
@@ -159,7 +143,7 @@ long int initdram (int board_type)
 /*     debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);  */
        } else {                                        /* back to 8 columns            */
                size_b0 = size8;
-               memctl->memc_mamr = CFG_MAMR_8COL;
+               memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
                udelay (500);
 /*     debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);  */
        }
@@ -172,7 +156,7 @@ long int initdram (int board_type)
         */
        if ((size_b0 < 0x02000000)) {
                /* reduce to 15.6 us (62.4 us / quad) */
-               memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+               memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
                udelay (1000);
        }
 
@@ -180,12 +164,12 @@ long int initdram (int board_type)
         * Final mapping
         */
 
-       memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-       memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+       memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+       memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
        /* adjust refresh rate depending on SDRAM type, one bank */
        reg = memctl->memc_mptpr;
-       reg >>= 1;                                      /* reduce to CFG_MPTPR_1BK_8K / _4K */
+       reg >>= 1;                                      /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
        memctl->memc_mptpr = reg;
 
        udelay (10000);
@@ -206,7 +190,7 @@ long int initdram (int board_type)
 static long int dram_size (long int mamr_value, long int *base,
                                                   long int maxsize)
 {
-       volatile immap_t *immap = (immap_t *) CFG_IMMR;
+       volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
 
        memctl->memc_mamr = mamr_value;