#define SDRAM_SIZE PHYS_SDRAM_1_SIZE
#endif
-#define REG_CCOSR 0x60
#define REG_CCGR0 0x68
#define REG_CCGR1 0x6c
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000)
MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000)
-#if 1
- MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCOSR, (1 << 24) | (0xe << 16))
- MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x320, 0x4) /* GPIO_3 => CLKO2 */
-#endif
+
MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */
MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */