check_cpu_temperature(1);
}
+#define LTC3676_BUCK1 0x01
+#define LTC3676_BUCK2 0x02
+#define LTC3676_BUCK3 0x03
+#define LTC3676_BUCK4 0x04
+#define LTC3676_DVB1A 0x0A
+#define LTC3676_DVB1B 0x0B
#define LTC3676_DVB2A 0x0C
#define LTC3676_DVB2B 0x0D
+#define LTC3676_DVB3A 0x0E
+#define LTC3676_DVB3B 0x0F
#define LTC3676_DVB4A 0x10
#define LTC3676_DVB4B 0x11
+#define LTC3676_MSKPG 0x13
+#define LTC3676_CLIRQ 0x1f
+
+#define LTC3676_BUCK_DVDT_FAST (1 << 0)
+#define LTC3676_BUCK_KEEP_ALIVE (1 << 1)
+#define LTC3676_BUCK_CLK_RATE_LOW (1 << 2)
+#define LTC3676_BUCK_PHASE_SEL (1 << 3)
+#define LTC3676_BUCK_ENABLE_300 (1 << 4)
+#define LTC3676_BUCK_PULSE_SKIP (0 << 5)
+#define LTC3676_BUCK_BURST_MODE (1 << 5)
+#define LTC3676_BUCK_CONTINUOUS (2 << 5)
+#define LTC3676_BUCK_ENABLE (1 << 7)
+
+#define LTC3676_PGOOD_MASK (1 << 5)
+
+#define LTC3676_MSKPG_BUCK1 (1 << 0)
+#define LTC3676_MSKPG_BUCK2 (1 << 1)
+#define LTC3676_MSKPG_BUCK3 (1 << 2)
+#define LTC3676_MSKPG_BUCK4 (1 << 3)
+#define LTC3676_MSKPG_LDO2 (1 << 5)
+#define LTC3676_MSKPG_LDO3 (1 << 6)
+#define LTC3676_MSKPG_LDO4 (1 << 7)
+
+#define VDD_IO_VAL mV_to_regval(vout_to_vref(3300 * 10, 5))
+#define VDD_IO_VAL_LP mV_to_regval(vout_to_vref(3100 * 10, 5))
+#define VDD_IO_VAL_2 mV_to_regval(vout_to_vref(3300 * 10, 5_2))
+#define VDD_IO_VAL_2_LP mV_to_regval(vout_to_vref(3100 * 10, 5_2))
+#define VDD_SOC_VAL mV_to_regval(vout_to_vref(1425 * 10, 6))
+#define VDD_SOC_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 6))
+#define VDD_DDR_VAL mV_to_regval(vout_to_vref(1500 * 10, 7))
+#define VDD_CORE_VAL mV_to_regval(vout_to_vref(1425 * 10, 8))
+#define VDD_CORE_VAL_LP mV_to_regval(vout_to_vref(900 * 10, 8))
+
+/* LDO1 */
+#define R1_1 470
+#define R2_1 150
+/* LDO4 */
+#define R1_4 470
+#define R2_4 150
+/* Buck1 */
+#define R1_5 390
+#define R2_5 110
+#define R1_5_2 470
+#define R2_5_2 150
+/* Buck2 */
+#define R1_6 150
+#define R2_6 180
+/* Buck3 */
+#define R1_7 150
+#define R2_7 140
+/* Buck4 */
+#define R1_8 150
+#define R2_8 180
+
+/* calculate voltages in 10mV */
+#define R1(idx) R1_##idx
+#define R2(idx) R2_##idx
+
+#define vout_to_vref(vout, idx) ((vout) * R2(idx) / (R1(idx) + R2(idx)))
+#define vref_to_vout(vref, idx) DIV_ROUND_UP((vref) * (R1(idx) + R2(idx)), R2(idx))
+
+#define mV_to_regval(mV) DIV_ROUND(((((mV) < 4125) ? 4125 : (mV)) - 4125), 125)
+#define regval_to_mV(v) (((v) * 125 + 4125))
+
+static struct ltc3673_regs {
+ u8 addr;
+ u8 val;
+ u8 mask;
+} ltc3676_regs[] = {
+ { LTC3676_MSKPG, ~LTC3676_MSKPG_BUCK1, },
+ { LTC3676_DVB2B, VDD_SOC_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB3B, VDD_DDR_VAL, ~0x3f, },
+ { LTC3676_DVB4B, VDD_CORE_VAL | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB2A, VDD_SOC_VAL, ~0x3f, },
+ { LTC3676_DVB3A, VDD_DDR_VAL, ~0x3f, },
+ { LTC3676_DVB4A, VDD_CORE_VAL, ~0x3f, },
+ { LTC3676_BUCK1, LTC3676_BUCK_BURST_MODE | LTC3676_BUCK_CLK_RATE_LOW, },
+ { LTC3676_BUCK2, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_BUCK3, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_BUCK4, LTC3676_BUCK_BURST_MODE, },
+ { LTC3676_CLIRQ, 0, }, /* clear interrupt status */
+};
+
+static struct ltc3673_regs ltc3676_regs_1[] = {
+ { LTC3676_DVB1B, VDD_IO_VAL_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB1A, VDD_IO_VAL, ~0x3f, },
+};
+
+static struct ltc3673_regs ltc3676_regs_2[] = {
+ { LTC3676_DVB1B, VDD_IO_VAL_2_LP | LTC3676_PGOOD_MASK, ~0x3f, },
+ { LTC3676_DVB1A, VDD_IO_VAL_2, ~0x3f, },
+};
+
+static int tx6_rev_2(void)
+{
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank5_regs *fuse = (void *)ocotp->bank[5].fuse_regs;
+ u32 pad_settings = readl(&fuse->pad_settings);
+
+ debug("Fuse pad_settings @ %p = %02x\n",
+ &fuse->pad_settings, pad_settings);
+ return pad_settings & 1;
+}
+
+static int tx6_ltc3676_setup_regs(struct ltc3673_regs *r, size_t count)
+{
+ int ret;
+ int i;
-#define VDD_SOC_mV (1375 + 50)
-#define VDD_CORE_mV (1375 + 50)
+ for (i = 0; i < count; i++, r++) {
+#ifdef DEBUG
+ unsigned char value;
-#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25)
-#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360)
+ ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1);
+ if ((value & ~r->mask) != r->val) {
+ printf("Changing PMIC reg %02x from %02x to %02x\n",
+ r->addr, value, r->val);
+ }
+ if (ret) {
+ printf("%s: failed to read PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+#endif
+ ret = i2c_write(CONFIG_SYS_I2C_SLAVE,
+ r->addr, 1, &r->val, 1);
+ if (ret) {
+ printf("%s: failed to write PMIC register %02x: %d\n",
+ __func__, r->addr, ret);
+ return ret;
+ }
+ }
+ return 0;
+}
static int setup_pmic_voltages(void)
{
int ret;
unsigned char value;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
ret = i2c_probe(CONFIG_SYS_I2C_SLAVE);
if (ret != 0) {
printf("Failed to initialize I2C\n");
return ret;
}
- /* VDDCORE/VDDSOC default 1.375V is not enough, considering
- pfuze tolerance and IR drop and ripple, need increase
- to 1.425V for SabreSD */
-
- value = 0x39; /* VB default value & PGOOD not forced when slewing */
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1);
- if (ret) {
- printf("%s: failed to write PMIC DVB2B register: %d\n",
- __func__, ret);
- return ret;
- }
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1);
- if (ret) {
- printf("%s: failed to write PMIC DVB4B register: %d\n",
- __func__, ret);
- return ret;
- }
-
- value = mV_to_regval(VDD_SOC_mV);
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1);
- if (ret) {
- printf("%s: failed to write PMIC DVB2A register: %d\n",
- __func__, ret);
+ ret = tx6_ltc3676_setup_regs(ltc3676_regs, ARRAY_SIZE(ltc3676_regs));
+ if (ret)
return ret;
- }
- printf("VDDSOC set to %dmV\n", regval_to_mV(value));
- value = mV_to_regval(VDD_CORE_mV);
- ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1);
- if (ret) {
- printf("%s: failed to write PMIC DVB4A register: %d\n",
- __func__, ret);
- return ret;
+ printf("VDDCORE set to %umV\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(VDD_CORE_VAL), 8), 10));
+ printf("VDDSOC set to %umV\n",
+ DIV_ROUND(vref_to_vout(regval_to_mV(VDD_SOC_VAL), 6), 10));
+
+ if (tx6_rev_2()) {
+ ret = tx6_ltc3676_setup_regs(ltc3676_regs_2,
+ ARRAY_SIZE(ltc3676_regs_2));
+ printf("VDDIO set to %umV\n",
+ DIV_ROUND(vref_to_vout(
+ regval_to_mV(VDD_IO_VAL_2), 5_2), 10));
+ } else {
+ ret = tx6_ltc3676_setup_regs(ltc3676_regs_1,
+ ARRAY_SIZE(ltc3676_regs_1));
}
- printf("VDDCORE set to %dmV\n", regval_to_mV(value));
- return 0;
+ return ret;
}
int board_early_init_f(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000;
-#ifdef CONFIG_OF_LIBFDT
gd->bd->bi_arch_number = -1;
-#else
- gd->bd->bi_arch_number = 4429;
-#endif
+
+ if (ctrlc()) {
+ printf("CTRL-C detected; Skipping PMIC setup\n");
+ return 1;
+ }
+
ret = setup_pmic_voltages();
if (ret) {
printf("Failed to setup PMIC voltages\n");
static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg)
{
- void *p = cfg;
-
- return p - offsetof(struct tx6_esdhc_cfg, cfg);
+ return container_of(cfg, struct tx6_esdhc_cfg, cfg);
}
int board_mmc_getcd(struct mmc *mmc)
struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i];
int ret;
- if (i >= CONFIG_SYS_FSL_ESDHC_NUM)
- break;
-
cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid);
imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads);
};
#ifdef CONFIG_LCD
+static u16 tx6_cmap[256];
vidinfo_t panel_info = {
/* set to max. size supported by SoC */
.vl_col = 1920,
.vl_row = 1080,
.vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */
+ .cmap = tx6_cmap,
};
static struct fb_videomode tx6_fb_modes[] = {
+#ifndef CONFIG_SYS_LVDS_IF
{
/* Standard VGA timing */
.name = "VGA",
.lower_margin = 525 - 480 - 35,
.sync = FB_SYNC_CLK_LAT_FALL,
},
+#else
+ {
+ /* HannStar HSD100PXN1
+ * 202.7m mm x 152.06 mm display area.
+ */
+ .name = "HSD100PXN1",
+ .refresh = 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = KHZ2PICOS(65000),
+ .left_margin = 0,
+ .hsync_len = 0,
+ .right_margin = 320,
+ .upper_margin = 0,
+ .vsync_len = 0,
+ .lower_margin = 38,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ },
+#endif
{
/* unnamed entry for assigning parameters parsed from 'video_mode' string */
.refresh = 60,
};
static int lcd_enabled = 1;
+static int lcd_bl_polarity;
+
+static int lcd_backlight_polarity(void)
+{
+ return lcd_bl_polarity;
+}
void lcd_enable(void)
{
udelay(100);
gpio_set_value(TX6_LCD_RST_GPIO, 1);
udelay(300000);
- gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0);
+ gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+ lcd_backlight_polarity());
}
}
{
if (lcd_enabled) {
debug("Switching LCD off\n");
- gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1);
+ gpio_set_value(TX6_LCD_BACKLIGHT_GPIO,
+ !lcd_backlight_polarity());
gpio_set_value(TX6_LCD_RST_GPIO, 0);
gpio_set_value(TX6_LCD_PWR_GPIO, 0);
}
void lcd_ctrl_init(void *lcdbase)
{
int color_depth = 24;
- char *vm;
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
+ const char *vm;
unsigned long val;
int refresh = 60;
struct fb_videomode *p = &tx6_fb_modes[0];
struct fb_videomode fb_mode;
int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0;
- int pix_fmt = 0;
- ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3;
+ int pix_fmt;
+ int lcd_bus_width;
unsigned long di_clk_rate = 65000000;
if (!lcd_enabled) {
return;
}
- if (tstc() || (wrsr & WRSR_TOUT)) {
+ if (had_ctrlc() || (wrsr & WRSR_TOUT)) {
debug("Disabling LCD\n");
lcd_enabled = 0;
+ setenv("splashimage", NULL);
return;
}
karo_fdt_move_fdt();
+ lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt);
- vm = getenv("video_mode");
- if (vm == NULL) {
+ if (video_mode == NULL) {
debug("Disabling LCD\n");
lcd_enabled = 0;
return;
}
- if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) {
+ vm = video_mode;
+ if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) {
p = &fb_mode;
debug("Using video mode from FDT\n");
vm += strlen(vm);
switch (val) {
case 32:
case 24:
- if (pix_fmt == IPU_PIX_FMT_LVDS666)
+ if (is_lvds())
pix_fmt = IPU_PIX_FMT_LVDS888;
/* fallthru */
case 16:
break;
case 18:
- if (pix_fmt == IPU_PIX_FMT_LVDS666) {
+ if (is_lvds()) {
color_depth = val;
break;
}
break;
default:
- if (!pix_fmt) {
- char *tmp;
-
- if (strncmp(vm, "LVDS", 4) == 0) {
- pix_fmt = IPU_PIX_FMT_LVDS666;
- di_clk_parent = DI_PCLK_LDB;
- } else {
- pix_fmt = IPU_PIX_FMT_RGB24;
- }
- tmp = strchr(vm, ':');
- if (tmp)
- vm = tmp;
- }
if (*vm != '\0')
vm++;
}
p->pixclock = KHZ2PICOS(refresh *
(p->xres + p->left_margin + p->right_margin + p->hsync_len) *
- (p->yres + p->upper_margin + p->lower_margin + p->vsync_len)
- / 1000);
+ (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) /
+ 1000);
debug("Pixel clock set to %lu.%03lu MHz\n",
- PICOS2KHZ(p->pixclock) / 1000,
- PICOS2KHZ(p->pixclock) % 1000);
+ PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000);
if (p != &fb_mode) {
int ret;
- char *modename = getenv("video_mode");
- printf("Creating new display-timing node from '%s'\n",
- modename);
- ret = karo_fdt_create_fb_mode(working_fdt, modename, p);
+ debug("Creating new display-timing node from '%s'\n",
+ video_mode);
+ ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p);
if (ret)
printf("Failed to create new display-timing node from '%s': %d\n",
- modename, ret);
+ video_mode, ret);
}
gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios));
imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads,
ARRAY_SIZE(stk5_lcd_pads));
- debug("Initializing FB driver\n");
- if (!pix_fmt)
- pix_fmt = IPU_PIX_FMT_RGB24;
- else if (pix_fmt == IPU_PIX_FMT_LVDS666) {
- writel(0x01, IOMUXC_BASE_ADDR + 8);
- } else if (pix_fmt == IPU_PIX_FMT_LVDS888) {
- writel(0x21, IOMUXC_BASE_ADDR + 8);
- }
- if (pix_fmt != IPU_PIX_FMT_RGB24) {
- struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* enable LDB & DI0 clock */
- writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK |
- MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK,
- &ccm_regs->CCGR3);
+ lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24);
+ switch (lcd_bus_width) {
+ case 24:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS888 : IPU_PIX_FMT_RGB24;
+ break;
+
+ case 18:
+ pix_fmt = is_lvds() ? IPU_PIX_FMT_LVDS666 : IPU_PIX_FMT_RGB666;
+ break;
+
+ case 16:
+ if (!is_lvds()) {
+ pix_fmt = IPU_PIX_FMT_RGB565;
+ break;
+ }
+ /* fallthru */
+ default:
+ lcd_enabled = 0;
+ printf("Invalid %s bus width: %d\n", is_lvds() ? "LVDS" : "LCD",
+ lcd_bus_width);
+ return;
}
+ if (is_lvds()) {
+ int lvds_mapping = karo_fdt_get_lvds_mapping(working_fdt, 0);
+ int lvds_chan_mask = karo_fdt_get_lvds_channels(working_fdt);
+ uint32_t gpr2;
+ if (lvds_chan_mask == 0) {
+ printf("No LVDS channel active\n");
+ lcd_enabled = 0;
+ return;
+ }
+
+ gpr2 = (lvds_mapping << 6) | (lvds_mapping << 8);
+ if (lcd_bus_width == 24)
+ gpr2 |= (1 << 5) | (1 << 7);
+ gpr2 |= (lvds_chan_mask & 1) ? 1 << 0 : 0;
+ gpr2 |= (lvds_chan_mask & 2) ? 3 << 2 : 0;
+ debug("writing %08x to GPR2[%08x]\n", gpr2, IOMUXC_BASE_ADDR + 8);
+ writel(gpr2, IOMUXC_BASE_ADDR + 8);
+ }
if (karo_load_splashimage(0) == 0) {
+ int ret;
+
debug("Initializing LCD controller\n");
- ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1);
+ ret = ipuv3_fb_init(p, 0, pix_fmt, DI_PCLK_PLL3, di_clk_rate, -1);
+ if (ret) {
+ printf("Failed to initialize FB driver: %d\n", ret);
+ lcd_enabled = 0;
+ }
} else {
debug("Skipping initialization of LCD controller\n");
}
{
unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0);
- if (tstc() || (wrsr & WRSR_TOUT))
+ if (had_ctrlc() || (wrsr & WRSR_TOUT))
return;
if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000)
printf("CPU clock set to %lu.%03lu MHz\n",
cpu_clk / 1000000, cpu_clk / 1000 % 1000);
} else {
- printf("Failed to set CPU clock to %lu MHz\n", cpu_clk);
+ printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk);
}
}
return;
}
- eth_setenv_enetaddr("ethaddr", mac);
printf("MAC addr from fuse: %pM\n", mac);
+ eth_setenv_enetaddr("ethaddr", mac);
}
int board_late_init(void)
tx6_init_mac();
gpio_set_value(TX6_RESET_OUT_GPIO, 1);
+ clear_ctrlc();
return ret;
}
tx6qdl_print_cpuinfo();
- printf("Board: Ka-Ro TX6%c-%dxx%d\n",
+ printf("Board: Ka-Ro TX6%c-%d%d1%d\n",
cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U',
cpu_variant == MXC_CPU_MX6Q ? 1 : 8,
- 1 - PHYS_SDRAM_1_WIDTH / 64);
+ is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64);
return 0;
}
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
#include <jffs2/jffs2.h>
#include <mtd_node.h>
-struct node_info nodes[] = {
+static struct node_info nodes[] = {
{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
};
-
#else
#define fdt_fixup_mtdparts(b,n,c) do { } while (0)
#endif
+static const char *tx6_touchpanels[] = {
+ "ti,tsc2007",
+ "edt,edt-ft5x06",
+ "eeti,egalax_ts",
+};
+
void ft_board_setup(void *blob, bd_t *bd)
{
const char *baseboard = getenv("baseboard");
int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0);
+ const char *video_mode = karo_get_vmode(getenv("video_mode"));
- karo_fdt_enable_node(blob, "stk5led", !stk5_v5);
+ if (stk5_v5)
+ karo_fdt_enable_node(blob, "stk5led", 0);
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
fdt_fixup_ethernet(blob);
- karo_fdt_fixup_touchpanel(blob);
+ karo_fdt_fixup_touchpanel(blob, tx6_touchpanels,
+ ARRAY_SIZE(tx6_touchpanels));
karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy");
karo_fdt_fixup_flexcan(blob, stk5_v5);
- karo_fdt_update_fb_mode(blob, getenv("video_mode"));
+
+ karo_fdt_update_fb_mode(blob, video_mode);
}
#endif /* CONFIG_OF_BOARD_SETUP */