/* ETN PHY Power */
MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015)
MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0)
- MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x000336c1 */
+ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */
MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */
#else
MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(1)) /* default: 0x00fc3003 USDHC1 */
#endif
- MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
-
- MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */
- MXC_DCD_ITEM(0x020c80b0, 0x00065b9a)
- MXC_DCD_ITEM(0x020c80c0, 0x000f4240)
+ MXC_DCD_ITEM(IOMUXC_GPR1, 0x00020000) /* default: 0x0f400005 ENET1_TX_CLK output */
+ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+ MXC_DCD_ITEM(0x020c80b0, 0)
+ MXC_DCD_ITEM(0x020c80c0, 1)
+ MXC_DCD_ITEM(0x020c80a0, 0x0010201b) /* set video PLL to 648MHz */
/* IOMUX: */
MXC_DCD_ITEM(IOMUXC_GPR0, 0x00000000)
MXC_DCD_ITEM(IOMUXC_GPR1, 0x0f460005) /* default: 0x0f400005 ENET1_TX_CLK output */