rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / board / lwmon5 / sdram.c

diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 7c3cf496be7f13cd6eea5b773bc66ba7bb4fec70..72968d78035240961f36eee324d79f64407adf96 100644 (file)
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -34,6 +34,7 @@
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/io.h>
+#include <asm/cache.h>
 #include <ppc440.h>
 #include <watchdog.h>
 
@@ -44,10 +45,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
 #define MY_TLB_WORD2_I_ENABLE  0                       /* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE  TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
@@ -59,7 +60,6 @@
 extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 extern void dcbz_area(u32 start_address, u32 num_bytes);
-extern void dflush(void);
 
 static u32 is_ecc_enabled(void)
 {
@@ -84,7 +84,7 @@ void board_add_ram_info(int use_default)
                puts(" (ECC not");
 
        get_sys_info(&board_cfg);
-       printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
+       printf(" enabled, %ld MHz", (board_cfg.freqPLB * 2) / 1000000);
 
        mfsdram(DDR0_03, val);
        val = DDR0_03_CASLAT_DECODE(val);
@@ -106,6 +106,7 @@ static void program_ecc(u32 start_address,
 {
        u32 val;
        u32 current_addr = start_address;
+       u32 size;
        int bytes_remaining;
 
        sync();
@@ -115,7 +116,7 @@ static void program_ecc(u32 start_address,
         * Because of 440EPx errata CHIP 11, we don't touch the last 256
         * bytes of SDRAM.
         */
-       bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
+       bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
 
        /*
         * We have to write the ECC bytes by zeroing and flushing in smaller
@@ -123,12 +124,18 @@ static void program_ecc(u32 start_address,
         * watchdog.
         */
        while (bytes_remaining > 0) {
-               dcbz_area(current_addr, min((64 << 20), bytes_remaining));
+               size = min((64 << 20), bytes_remaining);
+
+               /* Write zero's to SDRAM */
+               dcbz_area(current_addr, size);
+
+               /* Write modified dcache lines back to memory */
+               clean_dcache_range(current_addr, current_addr + size);
+
                current_addr += 64 << 20;
                bytes_remaining -= 64 << 20;
                WATCHDOG_RESET();
        }
-       dflush();
 
        sync();
        wait_ddr_idle();
@@ -151,7 +158,7 @@ static void program_ecc(u32 start_address,
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
 #if 0 /* test-only: will remove this define later, when ECC problems are solved! */
        /* CL=3 */
@@ -245,29 +252,29 @@ long int initdram (int board_type)
        /* -----------------------------------------------------------+
         * Perform data eye search if requested.
         * ----------------------------------------------------------*/
-       program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+       program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
                    TLB_WORD2_I_ENABLE);
        denali_core_search_data_eye();
-       remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+       remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 #endif
 
        /*
         * Program tlb entries for this size (dynamic)
         */
-       program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+       program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
                    MY_TLB_WORD2_I_ENABLE);
 
        /*
         * Setup 2nd TLB with same physical address but different virtual address
         * with cache enabled. This is done for fast ECC generation.
         */
-       program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+       program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 
 #ifdef CONFIG_DDR_ECC
        /*
         * If ECC is enabled, initialize the parity bits.
         */
-       program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+       program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 #endif
 
        /*
@@ -277,5 +284,5 @@ long int initdram (int board_type)
         */
        set_mcsr(get_mcsr());
 
-       return (CFG_MBYTES_SDRAM << 20);
+       return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }