Merge branch 'master' of git://www.denx.de/git/u-boot-sh

[karo-tx-uboot.git] / board / ms7722se / lowlevel_init.S

diff --git a/board/ms7722se/lowlevel_init.S b/board/ms7722se/lowlevel_init.S
index e0d519c55a46694f972a45b575bd33ade79ecd7a..332f65a4ce1e41a86e5241da0f5b110eb75f7e42 100644 (file)
--- a/board/ms7722se/lowlevel_init.S
+++ b/board/ms7722se/lowlevel_init.S
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2007
  * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *    
+ *
  * Copyright (C) 2007
  * Kenati Technologies, Inc.
  *
@@ -52,19 +52,19 @@ lowlevel_init:
        mov.l   r0, @r1
 
        mov.l   MSTPCR0_A, r1   ! Address of Power Control Register 0
-       mov.l   MSTPCR0_D, r0   ! 
+       mov.l   MSTPCR0_D, r0   !
        mov.l   r0, @r1
 
        mov.l   MSTPCR2_A, r1   ! Address of Power Control Register 2
-       mov.l   MSTPCR2_D, r0   ! 
+       mov.l   MSTPCR2_D, r0   !
        mov.l   r0, @r1
 
-       mov.l   SBSCR_A, r1     ! 
-       mov.w   SBSCR_D, r0     ! 
+       mov.l   SBSCR_A, r1     !
+       mov.w   SBSCR_D, r0     !
        mov.w   r0, @r1
 
-       mov.l   PSCR_A, r1      ! 
-       mov.w   PSCR_D, r0      ! 
+       mov.l   PSCR_A, r1      !
+       mov.w   PSCR_D, r0      !
        mov.w   r0, @r1
 
 !      mov.l   RWTCSR_A, r1    ! 0xA4520004 (Watchdog Control / Status Register)
@@ -80,7 +80,7 @@ lowlevel_init:
        mov.w   r0, @r1
 
        mov.l   FRQCR_A, r1             ! 0xA4150000 Frequency control register
-       mov.l   FRQCR_D, r0     ! 
+       mov.l   FRQCR_D, r0     !
        mov.l   r0, @r1
 
        mov.l   CCR_A, r1               ! Address of Cache Control Register
@@ -114,11 +114,11 @@ bsc_init:
        mov.w   r0, @r1
 
        mov.l   CMNCR_A, r1     ! CMNCR address -> R1
-       mov.l   CMNCR_D, r0     ! CMNCR data    -> R0
+       mov.l   CMNCR_D, r0     ! CMNCR data    -> R0
        mov.l   r0, @r1         ! CMNCR set
 
        mov.l   CS0BCR_A, r1    ! CS0BCR address -> R1
-       mov.l   CS0BCR_D, r0    ! CS0BCR data    -> R0
+       mov.l   CS0BCR_D, r0    ! CS0BCR data    -> R0
        mov.l   r0, @r1         ! CS0BCR set
 
        mov.l   CS2BCR_A, r1    ! CS2BCR address -> R1
@@ -130,39 +130,39 @@ bsc_init:
        mov.l   r0, @r1         ! CS4BCR set
 
        mov.l   CS5ABCR_A, r1   ! CS5ABCR address -> R1
-       mov.l   CS5ABCR_D, r0   ! CS5ABCR data    -> R0
+       mov.l   CS5ABCR_D, r0   ! CS5ABCR data    -> R0
        mov.l   r0, @r1         ! CS5ABCR set
 
        mov.l   CS5BBCR_A, r1   ! CS5BBCR address -> R1
-       mov.l   CS5BBCR_D, r0   ! CS5BBCR data    -> R0
+       mov.l   CS5BBCR_D, r0   ! CS5BBCR data    -> R0
        mov.l   r0, @r1         ! CS5BBCR set
 
        mov.l   CS6ABCR_A, r1   ! CS6ABCR address -> R1
-       mov.l   CS6ABCR_D, r0   ! CS6ABCR data    -> R0
+       mov.l   CS6ABCR_D, r0   ! CS6ABCR data    -> R0
        mov.l   r0, @r1         ! CS6ABCR set
 
        mov.l   CS0WCR_A, r1    ! CS0WCR address -> R1
-       mov.l   CS0WCR_D, r0    ! CS0WCR data    -> R0
+       mov.l   CS0WCR_D, r0    ! CS0WCR data    -> R0
        mov.l   r0, @r1         ! CS0WCR set
 
        mov.l   CS2WCR_A, r1    ! CS2WCR address -> R1
-       mov.l   CS2WCR_D, r0    ! CS2WCR data    -> R0
+       mov.l   CS2WCR_D, r0    ! CS2WCR data    -> R0
        mov.l   r0, @r1         ! CS2WCR set
 
        mov.l   CS4WCR_A, r1    ! CS4WCR address -> R1
-       mov.l   CS4WCR_D, r0    ! CS4WCR data    -> R0
+       mov.l   CS4WCR_D, r0    ! CS4WCR data    -> R0
        mov.l   r0, @r1         ! CS4WCR set
 
        mov.l   CS5AWCR_A, r1   ! CS5AWCR address -> R1
-       mov.l   CS5AWCR_D, r0   ! CS5AWCR data    -> R0
+       mov.l   CS5AWCR_D, r0   ! CS5AWCR data    -> R0
        mov.l   r0, @r1         ! CS5AWCR set
 
        mov.l   CS5BWCR_A, r1   ! CS5BWCR address -> R1
-       mov.l   CS5BWCR_D, r0   ! CS5BWCR data    -> R0
+       mov.l   CS5BWCR_D, r0   ! CS5BWCR data    -> R0
        mov.l   r0, @r1         ! CS5BWCR set
 
        mov.l   CS6AWCR_A, r1   ! CS6AWCR address -> R1
-       mov.l   CS6AWCR_D, r0   ! CS6AWCR data    -> R0
+       mov.l   CS6AWCR_D, r0   ! CS6AWCR data    -> R0
        mov.l   r0, @r1         ! CS6AWCR set
 
        ! SDRAM initialization
@@ -187,7 +187,7 @@ bsc_init:
        mov.l   r0, @r1         ! SB_RTCSR set
 
        mov.l   SDMR3_A, r1     ! SDMR3 address -> R1
-       mov     #0x00, r0       ! SDMR3 data    -> R0
+       mov     #0x00, r0       ! SDMR3 data    -> R0
        mov.b   r0, @r1         ! SDMR3 set
 
        ! BL bit off (init = ON)  (?!?)
@@ -200,11 +200,9 @@ bsc_init:
        rts
        mov     #0, r0
 
-
-
        .align  2
 
-CCR_A:         .long   CCR                     
+CCR_A:         .long   CCR
 MMUCR_A:       .long   MMUCR
 MSTPCR0_A:     .long   MSTPCR0
 MSTPCR2_A:     .long   MSTPCR2
@@ -223,7 +221,7 @@ FRQCR_D:    .long   0x07022538
 
 PSELA_A:       .long   0xa405014E
 PSELA_D:       .word   0x0A10
-        .align 2
+       .align 2
 
 DRVCR_A:       .long   0xa405018A
 DRVCR_D:       .word   0x0554