* (C) Copyright 2008
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
/* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
- /* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */
+#if defined(CONFIG_HARD_I2C)
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
+#else
+ /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
+ /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
+#endif
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
- * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+ * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
*/
*sdmr_ptr = sdmr | PSDMR_OP_PREA;
*base = c;
*sdmr_ptr = sdmr | PSDMR_OP_MRW;
- *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */
+ *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
*base = c;
phys_size_t initdram (int board_type)
{
- volatile immap_t *immap = (immap_t *) CFG_IMMR;
+ volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
long psize;
-#ifndef CFG_RAMBOOT
long sizelittle, sizebig;
-#endif
- memctl->memc_psrt = CFG_PSRT;
- memctl->memc_mptpr = CFG_MPTPR;
+ memctl->memc_psrt = CONFIG_SYS_PSRT;
+ memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifndef CFG_RAMBOOT
/* 60x SDRAM setup:
*/
- sizelittle = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
- (uchar *) CFG_SDRAM_BASE);
- sizebig = try_init (memctl, CFG_PSDMR_BIG, CFG_OR1_BIG,
- (uchar *) CFG_SDRAM_BASE);
+ sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
+ sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
if (sizelittle < sizebig) {
psize = sizebig;
} else {
- psize = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
- (uchar *) CFG_SDRAM_BASE);
+ psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+ (uchar *) CONFIG_SYS_SDRAM_BASE);
}
-#endif /* CFG_RAMBOOT */
icache_enable ();
}
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
+DECLARE_GLOBAL_DATA_PTR;
+
/*
* update "memory" property in the blob
*/
void ft_blob_update (void *blob, bd_t *bd)
{
int ret, nodeoffset = 0;
- ulong memory_data[2] = {0};
ulong flash_data[4] = {0};
- ulong freq = 0;
ulong speed = 0;
- memory_data[0] = cpu_to_be32 (bd->bi_memstart);
- memory_data[1] = cpu_to_be32 (bd->bi_memsize);
-
- nodeoffset = fdt_path_offset (blob, "/memory");
- if (nodeoffset >= 0) {
- ret = fdt_setprop (blob, nodeoffset, "reg", memory_data,
- sizeof(memory_data));
- if (ret < 0)
- printf ("ft_blob_update): cannot set /memory/reg "
- "property err:%s\n", fdt_strerror (ret));
- } else {
- /* memory node is required in dts */
- printf ("ft_blob_update(): cannot find /memory node "
- "err:%s\n", fdt_strerror(nodeoffset));
- }
/* update Flash addr, size */
- flash_data[2] = cpu_to_be32 (CFG_FLASH_BASE);
- flash_data[3] = cpu_to_be32 (CFG_FLASH_SIZE);
+ flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+ flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
nodeoffset = fdt_path_offset (blob, "/localbus");
if (nodeoffset >= 0) {
ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
printf ("ft_blob_update(): cannot find /localbus node "
"err:%s\n", fdt_strerror (nodeoffset));
}
- /* MAC Adresse */
- nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
- if (nodeoffset >= 0) {
- ret = fdt_setprop (blob, nodeoffset, "mac-address", bd->bi_enetaddr,
- sizeof (uchar) * 6);
- if (ret < 0)
- printf ("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address "
- "property err:%s\n", fdt_strerror (ret));
- } else {
- /* memory node is required in dts */
- printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node "
- "err:%s\n", fdt_strerror (nodeoffset));
- }
-
- /* brg clock */
- nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg");
- if (nodeoffset >= 0) {
- freq = cpu_to_be32 (bd->bi_brgfreq);
- ret = fdt_setprop (blob, nodeoffset, "clock-frequency", &freq,
- sizeof (unsigned long));
- if (ret < 0)
- printf ("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency "
- "property err:%s\n", fdt_strerror (ret));
- } else {
- /* memory node is required in dts */
- printf ("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node "
- "err:%s\n", fdt_strerror (nodeoffset));
- }
/* baudrate */
nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
if (nodeoffset >= 0) {
- speed = cpu_to_be32 (bd->bi_baudrate);
+ speed = cpu_to_be32 (gd->baudrate);
ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
sizeof (unsigned long));
if (ret < 0)
}
}
-void ft_board_setup (void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup (blob, bd);
ft_blob_update (blob, bd);
+
+ return 0;
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */