* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <twl4030.h>
+#include <linux/mtd/nand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/omap_gpmc.h>
+#include <asm/omap_gpmc.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
{
int revision;
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ unsigned char data;
+
+ /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
+ /* these boards should return a revision number of 0 */
+ /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ data = 0x01;
+ i2c_write(0x4B, 0x29, 1, &data, 1);
+ data = 0x0c;
+ i2c_write(0x4B, 0x2b, 1, &data, 1);
+ i2c_read(0x4B, 0x2a, 1, &data, 1);
+#endif
+
if (!gpio_request(112, "") &&
!gpio_request(113, "") &&
!gpio_request(115, "")) {
return revision;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ switch (get_board_revision()) {
+ case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
+ timings->mcfg = MCFG(512 << 20, 15);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ default:
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
+#endif
+
/*
* Routine: get_sdio2_config
* Description: Return information about the wifi module connection
return rc;
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif