Merge branch 'u-boot/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / overo / overo.c

diff --git a/board/overo/overo.c b/board/overo/overo.c
index a6e2e935a7c3059f45c7e2d6a41efc403d34727c..9ac35d2f4e331056bff1b1359b270688444e97c2 100644 (file)
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -92,7 +92,7 @@ int get_board_revision(void)
 {
        int revision;
 
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
        unsigned char data;
 
        /* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
@@ -142,16 +142,22 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
                timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
                break;
        case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
-               timings->mcfg = MICRON_V_MCFG_165(256 << 20);
-               timings->ctrla = MICRON_V_ACTIMA_165;
-               timings->ctrlb = MICRON_V_ACTIMB_165;
-               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+               timings->ctrla = MICRON_V_ACTIMA_200;
+               timings->ctrlb = MICRON_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                break;
        case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
-               timings->mcfg = HYNIX_V_MCFG_165(256 << 20);
-               timings->ctrla = HYNIX_V_ACTIMA_165;
-               timings->ctrlb = HYNIX_V_ACTIMB_165;
-               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+               timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+               timings->ctrla = HYNIX_V_ACTIMA_200;
+               timings->ctrlb = HYNIX_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+               break;
+       case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
+               timings->mcfg = MCFG(512 << 20, 15);
+               timings->ctrla = MICRON_V_ACTIMA_200;
+               timings->ctrlb = MICRON_V_ACTIMB_200;
+               timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
                break;
        default:
                timings->mcfg = MICRON_V_MCFG_165(128 << 20);