* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <twl4030.h>
+#include <linux/mtd/nand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
-#include <asm/arch/gpio.h>
+#include <asm/omap_gpmc.h>
+#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
+DECLARE_GLOBAL_DATA_PTR;
+
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
*/
int board_init(void)
{
- DECLARE_GLOBAL_DATA_PTR;
-
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OVERO;
{
int revision;
- if (!omap_request_gpio(112) &&
- !omap_request_gpio(113) &&
- !omap_request_gpio(115)) {
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ unsigned char data;
+
+ /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
+ /* these boards should return a revision number of 0 */
+ /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
+ i2c_set_bus_num(TWL4030_I2C_BUS);
+ data = 0x01;
+ i2c_write(0x4B, 0x29, 1, &data, 1);
+ data = 0x0c;
+ i2c_write(0x4B, 0x2b, 1, &data, 1);
+ i2c_read(0x4B, 0x2a, 1, &data, 1);
+#endif
- omap_set_gpio_direction(112, 1);
- omap_set_gpio_direction(113, 1);
- omap_set_gpio_direction(115, 1);
+ if (!gpio_request(112, "") &&
+ !gpio_request(113, "") &&
+ !gpio_request(115, "")) {
- revision = omap_get_gpio_datain(115) << 2 |
- omap_get_gpio_datain(113) << 1 |
- omap_get_gpio_datain(112);
+ gpio_direction_input(112);
+ gpio_direction_input(113);
+ gpio_direction_input(115);
- omap_free_gpio(112);
- omap_free_gpio(113);
- omap_free_gpio(115);
+ revision = gpio_get_value(115) << 2 |
+ gpio_get_value(113) << 1 |
+ gpio_get_value(112);
} else {
- printf("Error: unable to acquire board revision GPIOs\n");
+ puts("Error: unable to acquire board revision GPIOs\n");
revision = -1;
}
return revision;
}
+#ifdef CONFIG_SPL_BUILD
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ timings->mr = MICRON_V_MR_165;
+ switch (get_board_revision()) {
+ case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ break;
+ case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
+ timings->mcfg = MCFG(512 << 20, 15);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ break;
+ default:
+ timings->mcfg = MICRON_V_MCFG_165(128 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_165;
+ timings->ctrlb = MICRON_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ }
+}
+#endif
+
/*
* Routine: get_sdio2_config
* Description: Return information about the wifi module connection
{
int sdio_direct;
- if (!omap_request_gpio(130) && !omap_request_gpio(139)) {
+ if (!gpio_request(130, "") && !gpio_request(139, "")) {
- omap_set_gpio_direction(130, 0);
- omap_set_gpio_direction(139, 1);
+ gpio_direction_output(130, 0);
+ gpio_direction_input(139);
sdio_direct = 1;
- omap_set_gpio_dataout(130, 0);
- if (omap_get_gpio_datain(139) == 0) {
- omap_set_gpio_dataout(130, 1);
- if (omap_get_gpio_datain(139) == 1)
+ gpio_set_value(130, 0);
+ if (gpio_get_value(139) == 0) {
+ gpio_set_value(130, 1);
+ if (gpio_get_value(139) == 1)
sdio_direct = 0;
}
- omap_free_gpio(130);
- omap_free_gpio(139);
+ gpio_direction_input(130);
} else {
- printf("Error: unable to acquire sdio2 clk GPIOs\n");
+ puts("Error: unable to acquire sdio2 clk GPIOs\n");
sdio_direct = -1;
}
switch (get_sdio2_config()) {
case 0:
- printf("Tranceiver detected on mmc2\n");
+ puts("Tranceiver detected on mmc2\n");
MUX_OVERO_SDIO2_TRANSCEIVER();
break;
case 1:
- printf("Direct connection on mmc2\n");
+ puts("Direct connection on mmc2\n");
MUX_OVERO_SDIO2_DIRECT();
break;
default:
- printf("Unable to detect mmc2 connection type\n");
+ puts("Unable to detect mmc2 connection type\n");
}
switch (get_expansion_id()) {
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
+ /* second lan chip */
+ enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
+ 0x2B000000, GPMC_SIZE_16M);
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
setenv("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
- printf("No EEPROM on expansion board\n");
+ puts("No EEPROM on expansion board\n");
break;
default:
- printf("Unrecognized expansion board\n");
+ puts("Unrecognized expansion board\n");
}
if (expansion_config.content == 1)
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
- /* second lan chip */
- enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4], 0x2B000000,
- GPMC_SIZE_16M);
-
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
&ctrl_base->gpmc_nadv_ale);
/* Make GPIO 64 as output pin and send a magic pulse through it */
- if (!omap_request_gpio(64)) {
- omap_set_gpio_direction(64, 0);
- omap_set_gpio_dataout(64, 1);
+ if (!gpio_request(64, "")) {
+ gpio_direction_output(64, 0);
+ gpio_set_value(64, 1);
udelay(1);
- omap_set_gpio_dataout(64, 0);
+ gpio_set_value(64, 0);
udelay(1);
- omap_set_gpio_dataout(64, 1);
+ gpio_set_value(64, 1);
}
}
#endif
return rc;
}
-#ifdef CONFIG_GENERIC_MMC
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
int board_mmc_init(bd_t *bis)
{
- omap_mmc_init(0);
- return 0;
+ return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif