*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/io.h>
-
+#include <i2c.h>
+#include <mb862xx.h>
+#include <video_fb.h>
#include "upm_table.h"
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[]; /* FLASH chips info */
+extern GraphicDevice mb862xx;
void local_bus_init (void);
ulong flash_get_size (ulong base, int banknum);
int checkboard (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-
- char *src;
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ char buf[64];
int f;
- char *s = getenv("serial#");
+ int i = getenv_f("serial#", buf, sizeof(buf));
+#ifdef CONFIG_PCI
+ char *src;
+#endif
puts("Board: Socrates");
- if (s != NULL) {
+ if (i > 0) {
puts(", serial# ");
- puts(s);
+ puts(buf);
}
putc('\n');
int misc_init_r (void)
{
- volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
-
/*
* Adjust flash start and offset to detected values
*/
/*
* Check if boot FLASH isn't max size
*/
- if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
- memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
- memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
+ if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+ set_lbc_or(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
+ set_lbc_br(0, gd->bd->bi_flashstart |
+ (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address
*/
- flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+ flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
}
/*
* Check if only one FLASH bank is available
*/
- if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
- memctl->or1 = 0;
- memctl->br1 = 0;
+ if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
+ set_lbc_or(1, 0);
+ set_lbc_br(1, 0);
/*
* Re-do flash protection upon new addresses
*/
flash_protect (FLAG_PROTECT_CLEAR,
gd->bd->bi_flashstart, 0xffffffff,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Monitor protection ON by default */
flash_protect (FLAG_PROTECT_SET,
- CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR,
CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
/* Redundant environment protection ON by default */
flash_protect (FLAG_PROTECT_SET,
CONFIG_ENV_ADDR_REDUND,
- CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
- &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+ CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
+ &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
}
return 0;
*/
void local_bus_init (void)
{
- volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
- volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
+ volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
uint lbc_mhz;
- uint lcrr = CFG_LBC_LCRR;
+ uint lcrr = CONFIG_SYS_LBC_LCRR;
get_sys_info (&sysinfo);
- clkdiv = lbc->lcrr & 0x0f;
- lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+ clkdiv = lbc->lcrr & LCRR_CLKDIV;
+ lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
/* Disable PLL bypass for Local Bus Clock >= 66 MHz */
if (lbc_mhz >= 66)
out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int));
- if (getenv("lime")) {
- /* Init UPMB for Lime controller access */
- out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
- upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
- }
+ /* Init UPMB for Lime controller access */
+ out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
+ upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int));
}
#if defined(CONFIG_PCI)
#ifdef CONFIG_BOARD_EARLY_INIT_R
int board_early_init_r (void)
{
- volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* set and reset the GPIO pin 2 which will reset the W83782G chip */
out_8((unsigned char*)&gur->gpoutdr, 0x3F );
#endif /* CONFIG_BOARD_EARLY_INIT_R */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, bd_t *bd)
{
u32 val[12];
int rc, i = 0;
val[i++] = gd->bd->bi_flashstart;
val[i++] = gd->bd->bi_flashsize;
- if (getenv("lime")) {
+ if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
/* Fixup LIME mapping */
val[i++] = 2; /* chip select number */
val[i++] = 0; /* always 0 */
- val[i++] = CFG_LIME_BASE;
- val[i++] = CFG_LIME_SIZE;
+ val[i++] = CONFIG_SYS_LIME_BASE;
+ val[i++] = CONFIG_SYS_LIME_SIZE;
}
/* Fixup FPGA mapping */
val[i++] = 3; /* chip select number */
val[i++] = 0; /* always 0 */
- val[i++] = CFG_FPGA_BASE;
- val[i++] = CFG_FPGA_SIZE;
+ val[i++] = CONFIG_SYS_FPGA_BASE;
+ val[i++] = CONFIG_SYS_FPGA_SIZE;
rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
val, i * sizeof(u32), 1);
if (rc)
printf("Unable to update localbus ranges, err=%s\n",
fdt_strerror(rc));
+
+ return 0;
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-#include <i2c.h>
-#include <mb862xx.h>
-#include <video_fb.h>
-
-#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C)
-#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038)
-#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC)
-/* Lime clock frequency */
-#define CFG_LIME_CLK_100MHZ 0x00000
-#define CFG_LIME_CLK_133MHZ 0x10000
-/* SDRAM parameter */
-#define CFG_LIME_MMR_VALUE 0x4157BA63
-
-#define DISPLAY_WIDTH 800
-#define DISPLAY_HEIGHT 480
#define DEFAULT_BRIGHTNESS 25
#define BACKLIGHT_ENABLE (1 << 31)
-extern GraphicDevice mb862xx;
-
static const gdc_regs init_regs [] =
{
{0x0100, 0x00010f00},
return init_regs;
}
-/* Returns Lime base address */
-unsigned int board_video_init (void)
+int lime_probe(void)
{
+ uint cfg_br2;
+ uint cfg_or2;
+ int type;
- if (!getenv("lime"))
- return 0;
+ cfg_br2 = get_lbc_br(2);
+ cfg_or2 = get_lbc_or(2);
- /*
- * Reset Lime controller
- */
- out_be32((void *)CFG_LIME_SRST, 0x1);
- udelay(200);
+ /* Configure GPCM for CS2 */
+ set_lbc_br(2, 0);
+ set_lbc_or(2, 0xfc000410);
+ set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
+
+ /* Get controller type */
+ type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
+
+ /* Restore previous CS2 configuration */
+ set_lbc_br(2, 0);
+ set_lbc_or(2, cfg_or2);
+ set_lbc_br(2, cfg_br2);
+
+ return (type == MB862XX_TYPE_LIME) ? 1 : 0;
+}
- /* Set Lime clock to 133MHz */
- out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ);
- /* Delay required */
- udelay(300);
- /* Set memory parameters */
- out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+/* Returns Lime base address */
+unsigned int board_video_init (void)
+{
+ if (!lime_probe())
+ return 0;
- mb862xx.winSizeX = DISPLAY_WIDTH;
- mb862xx.winSizeY = DISPLAY_HEIGHT;
+ mb862xx.winSizeX = 800;
+ mb862xx.winSizeY = 480;
mb862xx.gdfIndex = GDF_15BIT_555RGB;
mb862xx.gdfBytesPP = 2;
- return CFG_LIME_BASE;
+ return CONFIG_SYS_LIME_BASE;
}
#define W83782D_REG_CFG 0x40
{
u8 buf;
- if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
+ if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
return -1;
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
- buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
+ buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
buf | 0x80);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
- buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG);
- i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG,
+ buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
+ i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
(buf & 0xf4) | 0x01);
return 0;
}
u8 old_buf;
/* Select bank 0 */
- if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+ if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
goto err;
else
buf = old_buf & 0xf8;
- if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
goto err;
if (br > 0) {
/* PWMOUT1 duty cycle ctrl */
buf = 255 / (100 / br);
- if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
goto err;
/* LEDs on */
- reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+ reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
if (!(reg & BACKLIGHT_ENABLE));
- out_be32((void *)(CFG_FPGA_BASE + 0x0c),
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
reg | BACKLIGHT_ENABLE);
} else {
buf = 0;
- if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
goto err;
/* LEDs off */
- reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+ reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
reg &= ~BACKLIGHT_ENABLE;
- out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg);
+ out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
}
/* Restore previous bank setting */
- if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+ if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
goto err;
return;
projects / karo-tx-uboot.git / blobdiff